Aldec Rolls Out Riviera-PRO 2007.10 for ASIC/FPGA Verification
Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, announced the release of Riviera-PRO 2007.10, with expanded SystemVerilog (Verification) construct support and improved performance of VHDL, Verilog and mixed RTL simulation. This mixed-language design simulation environment supports VHDL, Verilog, SystemVerilog, and SystemC designs. Riviera-PRO supports multi-million gate HDL designs with industry proven simulation technology that is renowned for quality, accuracy and performance.
Riviera-PRO 2007.10 now supports the SystemVerilog constructs for classes and strings. These constructs are typically used in verification functions as specified by Accellera SystemVerilog 3.1a / IEEE Std 1800-2005. In addition, VHDL RTL simulation performance is 30% faster and Verilog RTL simulation performance is up to 60% faster on large designs as compared to the previous release.
Riviera-PRO is available in three new configurations LV, LVT and LVT-SV, all licenses are floating and support UNIX, Windows® and Linux 32/64.
Availability
Riviera-PRO 2007.10, is available today and is sold directly from Aldec and its authorized world-wide distributors.
About Aldec
Aldec, Inc., established in 1984, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux, Solaris and Windows platforms.
Riviera-PRO is a trademark of Aldec, Inc.
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