Verific Design Automation Gains Momentum with Netlist Only Parser

Verific Design Automation, best known for its Verilog, SystemVerilog and VHDL parsers and elaborators, said that its Netlist Only Parser is gaining momentum among electronic design automation (EDA) applications, especially from startup and emerging companies.

Verific’s Netlist Only Parser includes a Verilog netlist reader and a generic hierarchical netlist database to help reduce development time for products operating at the gate level rather than the register transfer level (RTL).

These netlist data structures are identical to those being produced by Verific’s RTL elaborators, though Netlist Only Parser inputs are restricted to either Verilog or EDIF netlists. The netlist data structures are organized as a directed graph, and take about 300 bytes per object. In a typical flow, a designer would first parse a Verilog or Liberty library, followed by one or more Verilog netlists. Once in the database, designers can access the information through an extensive set of application programming interfaces (APIs) and build their own application.

“Applications for the Netlist Only Parser vary, though we have seen ample activity in programmable fabrics,” states Rob Dekker, founder and president of Verific. “Quite often, these companies do not want to work with RTL yet, but their own design software for placement and routing starts at cell or gate level. Instead of developing this infrastructure all by themselves, they turn to Verific, license our proven gate-level data structures, and build their own system on top of that. Later on, they can upgrade to Verilog or VHDL and our RTL elaborator slides right into the system they have been building all along.”

Netlist data structures come with object manipulation such as addition/deletion of cells, wires and ports. It has full hierarchy support and includes group/ungroup commands. Existing attributes on netlists are preserved and vendor-specific attributes can be added at will. Complete line/file information on incoming netlists is maintained and a comprehensive error handler is included.

As with all of Verific products, the Netlist Only Parser is written in C++ and is shipped as source code.

About Verific Design Automation
Verific Design Automation was founded in 1999 by electronic design automation (EDA) industry veteran Rob Dekker. It develops and sells C++ source code-based SystemVerilog, Verilog and VHDL front ends — parsers, analyzers and elaborators — as well as a generic hierarchical netlist database for EDA applications. Verific’s technology has been licensed in many applications, combined shipping more than 45,000 end-user copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email:

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