Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, announced that Renesas Technology Corp., a leading worldwide semiconductor system solutions provider, has adopted the statistical static timing analysis (SSTA) technology from the Cadence(R) Encounter(R) digital IC design platform to be part of its next-generation design flow. This advanced statistical timing analysis and optimization technology—an integral part of the Cadence Encounter Timing System and SoC Encounter(TM) RTL-to-GDSII System—allows Renesas to accurately account for the effects of process variability in its leading-edge 45-nanometer digital designs. The benefits include reduced silicon-failure risk, improved design robustness and convergence, enhanced quality of silicon (QoS), significantly faster turnaround time and a streamlined sign-off flow.
Variations in manufacturing result in structural changes in devices and interconnects leading to deviations in their electrical behavior. At 65 nanometers and below, process control is difficult and, as a result, designs that pass traditional sign-off standards might fail in silicon due to process variations. The SSTA technology from Cadence helps prevent these catastrophic silicon failures. Traditional timing analysis accounts for process variations by introducing more aggressive gross guard-band and multiple analysis corners to model different process and environmental variation combinations. Encounter Timing System GXL supplements traditional corner-based methods with powerful and accurate SSTA technology that can account for the variability of process parameters in a single run.
“At advanced technology nodes, statistical timing analysis is necessary to eliminate excessive over-design while maximizing performance, and to allow trade-offs between performance, yield and price,” said Hisaharu Miwa, general manager, Design Technology Div., LSI Product Technology Unit at Renesas Technology Corp. “Over the course of nine months, we performed rigorous evaluations of all commercial SSTA solutions on the market using comprehensive evaluation criteria. The SSTA technology in the Cadence Encounter platform scored the highest with a winning combination of speed, accuracy, and timing optimization capabilities. Also, since it communicates smoothly with the Encounter implementation flow and accurately accounts for inter-die, within-die and intra-cell variations, it will help us to accelerate timing closure and sign-off.”
The Encounter platform’s fast and accurate SSTA and concurrent optimization technology correctly accounts for how process variation affects delay and leakage power. This allows design engineers to move beyond the artificial limitations on speed, area and power imposed by a traditional corner-based approach. The SSTA technology holistically models the effect that global, within-the-die, and random variations have on delay while significantly reducing the pessimism that causes traditional design methodologies to break down below 65 nanometers. The net result is fewer analysis corners, increased chip performance, and better silicon.
“With Statistical STA technology, Renesas designers will be able to unlock the true potential of smaller process technologies in their next generation flow,” said David Desharnais, product marketing group director, Encounter. “Moving to smaller technologies, especially below 65 nanometers, can be risky. The SSTA technology in Encounter Timing System GXL can relieve much of the pain for customers, such as Renesas, empowering them to maximize design performance with minimum power consumption.”
SSTA is available as part of Encounter Timing System GXL and SoC Encounter GXL system.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Cadence and Encounter are registered trademarks of Cadence Design Systems, Inc, and SoC Encounterand the Cadence logo are trademarks of Cadence in the United States and other countries.