Denali, Tokyo Electron Device Create DFI DDR2 SDRAM PHY for Xilinx FPGA

Tokyo Electron Device, Ltd. (TED), an electronics technology and trading company focused on semiconductor products, and Denali Software, a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), announced the co-development and release of a DDR2 SDRAM PHY Design running on Virtex-5, the largest and fastest FPGA in the world, produced by Xilinx, Inc., compatible with DDR PHY Interface (DFI), which is the industry- standard interface for DDR memory controller and PHY.

The DDR PHY Interface (DFI) specification, developed by ARM, Denali, Intel, Rambus, Samsung, and Synopsys, defines a common interface between the DDR memory controller logic and the DDR PHY interface in order to reduce cost and expedite time-to-market for DDR DRAM memory system development. TED ASIC customers now have access to DDR PHY designs, in 90-nm process technologies and below, that integrate seamlessly with other DFI compatible designs, including Denali’s Databahn(TM) DDR memory controller products.

“We are delighted we could develop DFI DDR2 SDRAM PHY Design for Virtex-5, which is Xilinx’s state-of-the-art FPGA, with the support of Denali Software, Inc.,” remarked Masami Hasegawa, director and Xilinx product manager of Tokyo Electron Device, Ltd. “We expect this release will accelerate the promotion of Virtex-5 as well as our evaluation platform and design services in the world wide.”

“DFI certified “DDR2 SDRAM PHY Design” allows designers to develop large- scale integration (LSI) faster and with less risk,” stated Tadashi Arai, Director of Marketing Department, Xilinx KK. “We feel that Xilinx Virtex-5 FPGA and this PHY design provides designers with a more effective way for both ASIC Prototyping and mass-production with DDR2 controller design.”

Release of DDR2 SDRAM PHY helps to develop LSI faster with less risk using a high-speed DDR2 interface, relieving developers of time-consuming development and integration tasks needed for special designing of the DDR memory controller. Combining DDR2 SDRAM PHY and Denali’s Databahn memory controller design IP, featuring technology proven in LSI implementation and Tokyo Electron Device’s “inrevium(TM)” brand “Virtex-5 Multi-Application Evaluation Platform (TB-5V-LX110/220/330-DDR2),” developers can effectively improve the time-to-market cycle.

“As DDR DRAMs achieve speeds up to 1600 Mbps, high-performance DDR interfaces become a critical factor in overall system performance,” said Kenichi Sakamaki, General Manager of Denali Software K.K. “Designers, faced with challenges in achieving timing closure, need a complete, integrated solution consisting of digital DDR memory controllers and a DDR PHY that are proven and meet design requirements. The DFI specification provides a clean boundary between these two memory system components, and enables developers to use our high-quality, silicon-proven DDR IP solution for a broad set of process technologies. Tokyo Electron Device’s new DFI compatible DDR PHY designs are leading edge solutions for ASIC development, and provide customers with a meaningful advantage in DDR memory system development.”

About the DDR-PHY Interface (DFI) Specification
The memory controller logic and PHY interface represent the two primary design elements in DDR DRAM memory systems, which are used in virtually all electronic system designs, from mobile phones and set-top boxes, to computers and network routers. These two components of the memory system require a uniquely different set of engineering skills, tools and methodologies, and thus, are often developed by separate engineering teams, or are acquired from different third-party design intellectual property (IP) vendors.

The goal of the DFI specification is to define a common interface between the memory controller logic and the PHY interface in order to reduce cost, time-to-market, and increase the potential for reuse of the individual components that make up the memory system. The DFI specification is being developed by expert contributors from recognized leaders in the semiconductor, IP and electronic design automation (EDA) industries, including: ARM, Denali, Intel, Rambus, Samsung, and Synopsys.

The DFI specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the DRAM devices. The DFI Specification Rev 1.0 was released for production development in January 2007, and is available online.

About Tokyo Electron Device, Ltd.
Tokyo Electron Device, Ltd. is a technical trading company of electronic components devices focused on semiconductor products and computer network. Utilizing a rich background of experience in design and development technology at the design development center established in 1985, TED is actively engaged in developing “inrevium(TM)” brand products as well as commissioned design and development work.

About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry’s most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali’s EDA, IP and services to reduce risk and speed time-to- market for electronic system and chip design. Denali is headquartered in Palo Alto, California and has offices around the world to serve the global electronics industry.