SolidoSTAT Increases Yield of AMS, Custom Digital, Memory ICs

Solido Design Automation announced new software for the semiconductor industry that is a long-awaited answer to the problem of preventable parametric yield loss in integrated circuit design. The new software, called SolidoSTAT, launches a new class of electronic design automation software called “STAT” tools for transistor-level statistical design and verification.

Just as SPICE tools modernized transistor-level design in the late 20th century, STAT tools are needed for the coming generation of nanometer designs. According to Amit Gupta, Solido’s cofounder and CEO, as semiconductor process technologies and supply voltages shrink, microscopic local and global statistical variations adversely impact chip designs.

“Lower yields translate into higher costs and lower production capacity, and subtract from the bottom line for the most sought-after consumer electronics,” said Gupta. “The semiconductor industry can’t afford to operate with a handicap on supply. STAT tools provide a solution to this design/manufacturing problem.”

“Three goals of all design teams are to avoid yield loss and over-design, improve design robustness, and maximize designer productivity,” said Resve Saleh, NSERC/PMC-Sierra Chair Professor of Electrical and Computer Engineering at University of British Columbia. “When design teams achieve these goals, semiconductor companies and consumers win because it reduces their costs and gets products to market faster. Solido has produced an elegant solution to address these key areas for transistor-level nanometer designs.”

SolidoSTAT provides an efficient way for chip designers to gain insight into the effects of process variations on their design, and also to make the design more robust to these effects without over-designing.

For example, after using SolidoSTAT for one day on a filter design, a design team identified that variations in insertion loss, attenuation, and bandwidth were causing yield loss. SolidoSTAT pinpointed which devices and statistical variations were the source of the problem. It then automatically revealed better design options and identified the tradeoffs in attenuation, bandwidth, gain flatness, insertion loss, power, and total harmonic distortion that would improve yield. SolidoSTAT produced an acceptable path for improving yield to nearly 100 percent.

The SolidoSTAT suite includes five tools that add new capabilities to the IC design flow. These are the SolidoSTAT Sampler, Characterizer, Circuit Enhancer, Tradeoff Analyzer and Visualizer.

The SolidoSTAT Sampler accelerates traditional Monte Carlo analysis through parallel processing and high-efficiency sampling algorithms. Graphical output and data analysis provide answers to key design questions such as, “What are the problematic specifications and statistical distributions?” and “Which environmental conditions will cause problems in the design?”

The SolidoSTAT Characterizer uses patent-pending algorithms to pinpoint sources of yield and performance loss in the design, reducing the problem from thousands of parameters to just a handful of significant parameters. This multivariate approach flags sensitive devices and zeroes in on transistor, resistor and capacitor geometries that could be changed to improve the design.

The SolidoSTAT Circuit Enhancer automatically and intelligently explores sizing alternatives to improve the circuit’s robustness. Designers can compare candidate solutions and choose the one most suitable for their application.

The SolidoSTAT Tradeoff Analyzer mines Sampler results, without additional simulations, to identify tradeoffs between specifications that improve yield.

The SolidoSTAT Visualizer converts raw data from all the analyses into dynamic visual representations that offer designers key insight into their circuits.

The SolidoSTAT tool suite, which was previously commercially available on a limited basis, is now generally available immediately from Solido Design Automation. The software runs on Linux and Solaris operating systems.

About Solido Design Automation
Solido Design Automation Inc. provides transistor-level statistical design and verification software solutions for analog/mixed-signal, custom digital, and memory integrated circuits. Founded by serial analog entrepreneurs, the privately held company is headquartered in Saskatoon, Canada with sales offices in U.S.A., Japan and Europe. For further information, call 306-382-4100.