Averant, HDL Dynamics, KETI, PLS, Silicon Labs Join OCP-IP

Open Core Protocol International Partnership (OCP-IP) announced five new members: Averant, HDL Dynamics, Korea Electronics Technology Institute (KETI), PLS, and Silicon Laboratories. The new members represent a breadth of technologies, illustrating the combined industry-wide acceptance and adoption of the OCP standard.

Averant Inc., founded in 1997, is a privately held EDA firm pioneering new methodology and technologies for static formal verification. Averant’s flagship product is Solidify(TM), a robust formal verification engine that provides the basis for property-based design and protocol verification, and automatic design checks. These tools are easily adopted into the design flow, and help improve quality, reduce risk, and speed the design process.

Founded in 2000 and headquartered in Texas, HDL Dynamics is focused on solutions for emerging areas to SoC and multicore infrastructure and development. and offers a range of digital systems IP, including instrumentation blocks and customized cores and bus interfaces. HDL Dynamics provides both SoC and IP development and consulting services for RTL and ESL Design (including VHDL Verilog, and SystemC modeling and tooling), Design for Debug (OCP custom On-Silicon Instrumentation) and related areas of analysis and integration between instrumentation and EDA environments.

KETI, a specialized research institute in the electronics and information field, was established in 1991. The company contributes to the reinforcement of international competitiveness of the electronics, information and other related components industries by encouraging the R&D necessary for technological innovation and support of small and medium enterprises. KETI develops specialized areas and works to improve specialized research not only fostering special research on technology for venture, small and medium enterprises, but also R&D projects at the front of key technologies.

PLS Development Tools is one of the leading development tools manufactures of debug and emulators. These tools are specialized for the 16bit and 32bit microcontroller architectures SAB C16x, TriCore, Xscale, ARM7 and other ARM derivatives.

Silicon Laboratories is a leader in the innovation of high-performance, analog-intensive, and mixed-signal ICs. Headquartered in Austin, Texas, Silicon Labs is a global enterprise with worldwide operations, sales and design activities. Silicon Labs’ application specific and general purpose products serve a broad set of markets and applications including consumer, communications, computing, industrial and automotive. Silicon Labs is a fabless semiconductor company.

OCP-IP members receive free training and support, software tools, and documentation, enabling them to focus on the challenges of SoC design. Leveraging OCP-IP’s infrastructure eliminates the need to internally design, document, train and evolve a proprietary standard and accompanying support tools, freeing up critical resources for the real design work, while providing enormous cost savings.

“This new group of members represents a diverse set of product offerings, and highlights the broad OCP acceptance and adoption across many markets,” said Ian Mackintosh, president OCP-IP. “We are very proud to announce and welcome our new members, and look forward to working with them in the future.”

About OCP-IP
The OCP International Partnership Association, Inc. (OCP-IP), formed in 2001, promotes and supports the Open Core Protocol (OCP) as the complete socket standard ensuring rapid creation and integration of interoperable virtual components. OCP-IP’s Governing Steering Committee participants include: Nokia [NYSE:NOK], Texas Instruments [NYSE: TXN], Toshiba Semiconductor Group (including Toshiba America TAEC), and Sonics. OCP-IP is a non-profit corporation delivering the first fully supported, openly licensed, core-centric protocol comprehensively fulfilling system-level integration requirements. The OCP facilitates IP core reusability and reduces design time, risk, and manufacturing costs for SoC designs.