MediaTek, Apache Target 65nm, 45nm Physical Design Challenges

Apache Design Solutions, the technology leader in power signoff and complete silicon integrity platform solutions for system-on-chip (SoC), analog, and system designs, announced that MediaTek, a leading fabless semiconductor company for wireless communications and digital media solutions, has selected Apache as their EDA partner for addressing 65 and 45nm physical design challenges. The MediaTek-Apache collaboration will focus on areas of power and noise, including power signoff, advanced low power and leakage optimization, reliability methodology, thermal integrity, and IC-package noise management.

Through the MediaTek-Apache partnership, MediaTek plans to establish power and noise signoff flows for their 65/45nm high performance and low power designs based on Apache’s advanced technologies, as well as existing products such as RedHawk-EV, RedHawk-ALP, PsiWinder. Sahara-PTE, and Sentinel. In addition, MediaTek and Apache will share their expertise in methodology and signoff for system-on-chip (SoC) silicon integrity.

“At 65/45nm, we are seeing numerous designs with power and noise challenges, and forging a partnership with an EDA tools provider will enable us to manage and anticipate the upcoming needs,” said MediaTek. “Our collaboration with Apache gives us access to market leading signoff technologies and in-depth technical expertise from a world-class R&D and support team, which will help us gain greater confidence in the success of our 65 and 45nm tapeouts.”

“MediaTek is one of the leading fabless semiconductor companies and we are excited to partner with them in establishing signoff methodologies for their 65 and 45nm designs,” said Dian Yang, general manager and vice president of product management of Apache. “We look forward to the technical collaboration with MediaTek and developing new solutions for our silicon integrity platform that meet their current and future needs.”

About Apache’s Silicon Integrity Platform
Apache’s Silicon Integrity Platform (ASIP) is a fully integrated physical design analysis, debugging, and optimization platform that consider impact of all noise sources associated with advanced nanometer designs. ASIP considers concurrent and interdependent effects of advanced nanometer phenomena such as dynamic power, leakage, crosstalk, package/system IO, temperature, and substrate noise on silicon behavior to ensure first-silicon tapeout success. This vendor neutral platform enables designers to adopt any industry standard physical design flow, while providing a unified environment of extraction, characterization, simulation, and optimization for design analysis and optimization. ASIP addresses the following critical aspects of silicon integrity signoff.

RedHawk-EV with FAO
A full-chip Vectorless Dynamic power analysis and optimization solution addressing dynamic power issues such as simultaneous switching output (SSO) for core, memory, clock, and IO, as well as effects of on-chip inductance, package RLC, and decoupling capacitance. RedHawk with FAO automatically repairs sources of supply noise and optimizes designs to minimize power and leakage, while maintaining integrity.

A dynamic power integrity solution for ultra low power and leakage management designs utilizing advanced techniques such as MTCMOS, multi-Vth, LDO voltage regulators, and substrate back-biasing. RedHawk-ALP provides transient ramp-up (power-up) simulation for accurate performance vs. leakage optimization, as well as full-chip mixed-mode analysis.

A clock network integrity and critical path timing sign-off solution that considers the concurrent and interdependent effects of signal integrity (crosstalk noise) and power integrity (dynamic voltage drop and ground bounce) on clock network and critical path timing.

The industry’s first fully integrated power-thermal-electrical analysis and debugging solution for SoC designs with built-in power/noise/thermal library, an incremental RLC extraction for power, noise, and temperature, and tightly coupled high-capacity, high-performance power-thermal-electrical analysis engine.

The industry’s first combined chip-package-board power and I/O integrity solution addressing system-level power, I/O-SSO, and EMI challenges. Sentinel combines chip’s core switching power delivery network, I/O sub-system, and package / PCB models in a single environment for accurate IC-package co-design from early prototyping to signoff.

About Apache Design Solutions
Apache delivers the leading power sign-off solution adopted by 80% of top IDMs, fabless semiconductor companies, and foundries, as well as complete platform solution for silicon integrity of SoC, analog-IP, and system designs. Apache’s innovative platform considers all sources of noise that impacts the design — such as power, signal, package / system I/O, substrate, and temperature — Apache’s silicon integrity platform enables designers of leading networking, wireless, communication, consumer, and semiconductor companies to detect, fix, and prevent design weaknesses that can result in reduced yield or failed silicon / system. Apache’s vendor-neutral solutions enable designers to adopt any industry-standard physical design flow and are in production use by over 40 customers worldwide.

Apache Design Solutions, NSPICE, RedHawk, PsiWinder, Sahara-PTE, Sentinel, Vectorless Dynamic, and ASIP are trademarks of Apache Design Solutions, Inc.