Lattice Semiconductor Corporation (NASDAQ: LSCC) announced the industry’s lowest power XAUI/ HiGig(TM)/HiGig+(TM) to SPI4.2 programmable Fabric Interface Chip (FIC) solution implemented in its award-winning LatticeSCM(TM) FPGAs. The solution, which utilizes the LatticeSCM device’s System Packet Interface Level 4 Phase 2 (SPI4.2) hard IP capability, and includes Lattice’s 10Gigabit Ethernet Media Access Controller (MAC) soft IP core and the XAUI/HiGig/HiGig+ to SPI4.2 bridge design, provides a high-performance interface between the SERDES-based XAUI standard, used ubiquitously in 10G Ethernet networks, and SPI4.2, a very popular parallel bus interface used by Network Processor Unit (NPU) devices. When implemented in a LatticeSCM-15E FPGA packaged in a space-saving 256 fine pitch Ball Grid Array (fpBGA) package, the bridge solution requires a mere 17mm x 17mm on a printed circuit board while consuming only 2.5Watts of power, substantially less than competitive devices.
In support of the bridge functionality, the LatticeSCM devices include from 4- to 32-channels of high-speed SERDES capable of supporting data rates from 600Mbps to 3.8Gbps. The flexiPCS(TM) Physical Coding Sublayer block embedded in the devices supports an array of popular communications data protocols, including Gigabit Ethernet, Fibre Channel, 10 Gigabit Ethernet (XAUI), PCI Express, Serial RapidIO and SONET/SDH. As noted above, the LatticeSCM family also includes fully compliant embedded SPI4.2 controllers implemented in Lattice’s unique, low power Masked Array for Cost Optimization (MACO(TM)) structured ASIC technology. The combination of these features, along with the LatticeSCM device’s high-speed FPGA fabric and PURESPEED(TM) I/O technology, provides an ideal platform for a variety of Ethernet Service Card applications.
“Lattice has an excellent solution for bridging SPI4.2 to HiGig+,” said Brad Siim, VP of Engineering at Sandvine. “Their SCM15 device in a 256fpbga has the small footprint we were looking for. In addition, the low power consumption and proven interoperability made it the logical choice for our industry leading Policy Traffic Switch.”
“We are pleased that Lattice Semiconductor has reduced the time to market and development costs of building differentiated products based on Broadcom’s StrataXGSÒ Ethernet switches,” said Eric Hayes, Director of Marketing, Broadcom’s Enterprise Switching line of business. “Lattice has responded to the needs of our mutual customers by focusing on performance and low-power design while maintaining a small footprint with the LatticeSCM family.”
“We are very pleased to announce the release of our latest LatticeSCM-based bridge solution,” said Stan Kopec; Lattice corporate vice president of marketing. “The LatticeSCM family provides our customers with extremely flexible, high performance Ethernet bridging solutions that save substantial power, dramatically illustrating Lattice’s ‘More of the Best’ philosophy.”
Lattice’s unique Masked Array for Cost Optimization (MACO) embedded structured ASIC blocks are available on LatticeSCM FPGA devices and deliver pre-engineered, standard-compliant IP functions developed by Lattice to shorten end-system time to market. The enhanced MACO SPI4.2 blocks available on the LatticeSCM family of FPGAs are supported by Lattice’s latest generation of design tools, the recently announced ispLEVER(R) version 7.0 software design tool suite.
The LatticeSCM family, as well as the LatticeSC family, which does not support MACO functionality but is otherwise identical, provides 5 logic density points between 15K and 115K LUTs. Embedded memory capacity ranges from 1 to 7.8Megabits of dual-port block RAM with general-purpose 2Gbps PURESPEED I/O ranging from 139 to 942 I/O. Each device features 8 analog PLLs and 12 digital DLLs for optimum clock flexibility.
XAUI/HiGig/HiGig+ to SPI4.2 IP Bundle Now Available
The solution is available as a XAUI to SPI4.2 IP bundle downloadable from the Lattice Semiconductor website. This bundle demonstrates the power of the LatticeSCM family’s patented MACO technology along with its industry leading FPGA architecture. Key features of the IP bundle include:
- Supports full-duplex bridging between NPUs (SPI4.2) and Ethernet Switches (XAUI//HiGig/HiGig+)
- Supports XAUI standard data rate of 3.125Gbps on the SERDES as well as the HiGig+ data rate (3.8Gbps maximum SERDES frequency offers ample design margin)
- Supports flow control in both directions
- Supports various burst sizes
- Marks all packets with errors received before transmitting
- Supports statistics collection from the MAC
List price of the complete bundle including the MAC, the bridge design and SPI4.2 core, along with documentation, is $14,950.
An evaluation copy of the bundle is now available and can be downloaded by registered Lattice design tool users with up-to-date maintenance agreements without charge at Lattice Intellectual Property.
About Lattice Semiconductor
Lattice Semiconductor Corporation provides the industry’s broadest range of Programmable Logic Devices ( PLD), including Field Programmable Gate Arrays ( FPGA), Complex Programmable Logic Devices ( CPLD), Mixed-Signal Power Management and Clock Generation Devices, and industry-leading SERDES products. Lattice continues to deliver “More of the Best” to its customers with comprehensive solutions for system design, including an unequaled portfolio of high-performance, non-volatile and low-cost FPGAs. Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets.
Lattice Semiconductor Corporation, Lattice (& design), L (& design), flashBAK, LatticeMico32, LatticeXP, LatticeXP2, LatticeEC, LatticeECP, LatticeECP2, LatticeECP2M, LatticeSC, LatticeSCM, ispLEVER and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.