Xilinx, Inc. (Nasdaq: XLNX) announced the Xilinx Serial Connectivity Seminars, sponsored by industry leaders Agilent Technologies, Jungo, Linear Technology, Marvell, Mentor Graphics, and Nu Horizons Electronics. The Xilinx Serial Connectivity Seminars series is scheduled to run throughout North America September 11 – October 11, 2007.
The series is designed to present end-to-end connectivity solutions for implementing high-speed serial protocols from experts throughout the industry leveraging the high-performance features of Xilinx(R) Virtex(TM)-5 FPGAs. Separate PCI Express(R) integrated Endpoint block and Ethernet tracks allow attendees to maximize their time with a customized seminar schedule. Experts will be on hand to discuss specific design challenges and provide insight on serial connectivity tools and solutions.
Users may view live demonstrations of Xilinx development kits and get started on a path to serial design success by taking advantage of exclusive discounts of up to 30 percent on IP and kits available only to seminar attendees. Attendees can also sign up for hands-on workshops and register to win prizes at the conclusion of the seminar.
Serial I/O Design
- How to design and verify serial solutions in FPGAs: Attendees will learn about serial I/O design and verification through a sample design. This presentation will demonstrate how Xilinx(R) RocketIO(TM) GTP transceiver wizard can be used to choose the right parameters for Virtex(TM)-5 FPGA built-in transceivers and to test for bit-error rates for serial link integrity. Xilinx(R) ISE(TM) software and ChipScope(TM) Pro analyzer will be used.
- How to effectively test serial interfaces?: Serial interfaces require testing at several different layers within the protocol stack. It is essential that each of these layers is tested. Controlled stimulus is key to validating designs, from injecting CRC errors at the physical layer, testing flow control constraints at the data link layer, to testing performance at the transaction layer. During this interactive presentation, attendees will learn how to effectively test serial interfaces using a PCI Express integrated Endpoint block example application.
- Serial interconnect design (signal integrity) with RocketIO multi-gigabit serial transceivers (MGTs) and HyperLynx GHz: This session will focus on critical issues faced by designers while physically implementing serial channels on a PCB using Virtex-5 FPGA RocketIO MGTs and Mentor Graphics HyperLynx GHz. Issues discussed will range from crosstalk to the impact of vias, as well as methods for mitigating loss to ensure the design meets critical bit error rate requirements for PCI Express designs and other serial standards.
- Managing power when designing with multiple serial I/O lanes in FPGAs: This session will cover power management for FPGAs with built-in serial transceivers. With data transfers in multiple Gbps and multiple supply rails, managing system power is critical. Attendees will learn the key concepts of power management for high density FPGA designs with special emphasis on how to choose the right power supplies based on unique application requirements.
Integrated Endpoints for PCI Express Designs Track
- How to design PCI Express(R) applications with XilinxVirtex-5 FPGAs: This session will include an introduction to PCI Express architecture including topology, device drivers, and end applications. Attendees will: learn about the Virtex-5 FPGA’s integrated Endpoint blocks for PCI Express; create an example design using the CORE Generator(TM) software; simulate using Mentor ModelSim(TM); and implement using ISE design tools. Advanced topics will cover design considerations in integrating a core for a PCIe design, clocking, physical layer topics, DMA, and a performance bandwidth demonstration. The class will conclude with an application example (x1 PCIe Gigabit Ethernet).
- Building software drivers in integrated Endpoint blocks for PCI Express designs: This session will cover the WinDriver overview for PCI (including API overview), WinDriver demonstration including generating code for Xilinx devices, and an introduction and demonstration of working with Virtex-5 integrated Endpoint blocks for PCI Express designs.
Ethernet (GE and XAUI) Track
- How to design Gigabit Ethernet applications with Xilinx FPGAs: Gigabit Ethernet is the preferred standard for switching as well as a broad range of applications in industrial control, embedded, wired and wireless communications. In this session, attendees will learn about Gigabit Ethernet applications and how to use Xilinx Virtex-5 FPGAs to develop Ethernet applications using the built-in 10/100/1000 Ethernet MAC block with both a built-in transceiver and external PHY device. Design flow and system level concepts will be covered.
- How to design 10G Ethernet applications (10GE MAC and XAUI) with Xilinx Virtex-5 FPGAs (Includes Intro to XAUI): In this session, attendees will learn the details of designing a 10 Gigabit Ethernet System in Virtex-5 FPGAs. Attendees will learn about system design considerations for 10G Ethernet design, how to generate and simulate 10GEMAC, and XAUI cores using CORE Generator software and ModelSim tools. Advanced topics will cover core integration, clocking and physical layer aspects. The session will end with a hardware demonstration and application example.
Xilinx Serial Connectivity Seminars 2007
San Jose: Doubletree Hotel
Los Angeles: Marriott Manhattan Beach
Boston: Radisson Hotel (Chelmsford)
Montreal: Holiday Inn (Pointe-Claire)
Dallas: Renaissance Dallas (Richardson)
Chicago: Stonegate Conf. Center (Hoffman Estates)
San Jose: September 11, 2007
Los Angeles: September 13, 2007
Boston: September 26, 2007
Montreal: September 28, 2007
Dallas: October 9, 2007
Chicago: October 11, 2007
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