XJTAG announced that ARM (LSE:ARM) (Nasdaq:ARMHY) has selected the XJTAG boundary scan development system to improve and speed up the process of debugging and testing its range of ARM(R) RealView(R) development hardware tools, which include high-density, multi-layer development boards.
ARM is currently using XJTAG on its latest generation of RealView platform baseboards, which contain multiple high pin-count ball grid array (BGA) devices including processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs).
Spencer Saunders, engineering manager, platforms, System Design Division, ARM, said: “With tens of thousands of pins on each board, we recognised that it would not be possible to validate these circuits in a commercially realistic timescale without the use of a boundary scan test system. After evaluating the different competitive options, we selected the XJTAG boundary scan system due to its power, performance, versatility and cost effectiveness.”
The XJTAG system has enabled ARM to speed up the process of debug and test, get test coverage up to the 90 percent mark, achieve its ten-minutes-per-board boundary scan production test target, and to significantly improve production yields.
Simon Payne, CEO at XJTAG, said: “We are delighted that ARM, the world’s leading semiconductor intellectual property (IP) supplier, has selected the XJTAG system. With XJTAG, ARM engineers now have a boundary scan system that allows tests to be recorded, refined and repeatedly re-used throughout the development cycle both by its in-house team and contract manufacturing partners.”
ARM has developed a strong base of development tools, software and hardware products to support its system-on-chip IP. Its range of RealView development solutions are ideal systems for customers prototyping ARM processor-based products and are suitable for architecture and CPU evaluation, hardware and software development, and ASIC emulation.
XJTAG’s built-in design-for-test (DFT) functionality has enabled ARM to use the boundary scan system right from the very beginning of the development process to help improve the design and reduce respins. “XJTAG has saved ARM a great deal of time as it automatically handles any netlist changes by adapting to the new circuit connections, thereby avoiding the time-consuming process of manually picking through the netlist for errors,” added Joao De Oliveira, VP of business development at XJTAG.
The XJTAG development system is a cost-effective ‘out-of-the-box’ solution for debugging, testing and servicing electronic printed circuits boards and systems throughout the product lifecycle. The XJTAG system reduces the time and cost of board development and prototyping by allowing early test development, early design validation of CAD netlists, fast generation of highly functional tests and test re-use across circuits using the same devices.
XJTAG enables engineers to test a high proportion of the circuit (both boundary scan and cluster devices) including BGA and chip scale packages, such as SDRAMs, Ethernet controllers, video interfaces, Flash memories, FPGAs and microprocessors. XJTAG also enables In-System Programming of FPGAs, CPLDs and Flash memories.
For more information about the XJTAG system, please telephone +44 (0) 1954 213888, fax +44 (0) 1954 211565 or email email@example.com.
XJTAG is a leading supplier of IEEE Std. 1149.1 compliant boundary scan development tools. Its JTAG (Joint Test Action Group) development system offers a highly competitive solution for designers and developers of electronic printed circuit boards and systems. Utilising XJTAG allows the circuit development and prototyping process to be shortened significantly by facilitating early test development, early design validation, fast development of functional tests and test re-use across circuits that use the same devices. XJTAG is based in Cambridge, UK, and is part of the Cambridge Technology Group.
What is JTAG?
Advances in silicon design, such as increasing device density and, more recently, ball grid array (BGA) and chip scale packaging, have made traditional electronic circuit testing methods hard to use. In order to overcome these problems and others; some of the world’s leading silicon manufacturers combined to form the Joint Test Action Group (JTAG). The findings of this group were used as the basis for the Institute of Electrical and Electronic Engineers (IEEE) standard 1149.1: Standard Test Access Port and Boundary Scan Architecture.
ARM and RealView are registered trademarks of ARM Limited. “ARM” is used to represent ARM Holdings plc; its operating company ARM Limited; and the regional subsidiaries ARM INC.; ARM KK; ARM Korea Ltd.; ARM Taiwan; ARM France SAS; ARM Consulting (Shanghai) Co. Ltd.; ARM Belgium N.V.; AXYS Design Automation Inc.; AXYS GmbH; ARM Embedded Solutions Pvt. Ltd.; and ARM Physical IP, Inc.; and ARM Norway AS.