Apache Design Solutions, the leader in power signoff and complete silicon integrity platform solutions for system-on-chip (SoC) designs, announced that the company will present a technical paper on methodology for analysis and verification of power-gated circuits and designs at the ISLPED (International Symposium on Low Power Electronics and Design) 2007, being held August 27 – 29, 2007 in Portland, Oregon.
Apache Design Solutions, Inc.
Technical Paper: “A methodology for analysis and verification of power gated circuits and designs with correlated results”, presented by Kai Wang of Apache Design Solutions
Embassy Suites, 319 S.W. Pine Street, Portland, Oregon
Wednesday, August 29, 2007 – 11:15 AM – 12:45 PM
About Apache Design Solutions
Apache delivers the leading power sign-off solution adopted by 80% of top IDMs, fabless semiconductor companies, and foundries, as well as complete platform solutions for silicon integrity of SoC, analog-IP, and system designs. Apache’s innovative platform considers all sources of noise that impact the design–such as power, signal, package / system I/O, substrate, and temperature–Apache’s silicon integrity platform enables designers of leading networking, wireless, communication, consumer, and semiconductor companies to detect, fix, and prevent design weaknesses that can result in reduced yield or failed silicon / system. Apache’s vendor-neutral solutions enable designers to adopt any industry-standard physical design flow and are in production use by over 40 customers worldwide.