DVCon 2008 Call for Paper, Panel, Tutorial Proposals
The 2008 Design and Verification Conference (DVCon), sponsored by Accellera, is now accepting paper, panel and tutorial submissions. DVCon 2008 will be held February 19-21, 2008 at the DoubleTree Hotel in San Jose, California. “DVCon has grown to become the premier conference for design and functional verification,” commented Stephen Bailey, 2008 General Chair. “Attendance at DVCon 2007 exceeded all expectations and we anticipate continued attendance growth this year. DVCon is the place to learn what is new in methodology, tools and technology for addressing design and verification productivity and quality.”
Of special interest to the DVCon Technical Program Committee for the 2008 conference are topics such as: low-power design and verification, formal verification, multi-clock verification, design and verification case studies, verification and design release management, functional coverage and verification data management, verification methodology and testbenches, verification IP development, and appropriate academic and research information.
Paper and special session proposals are due September 19, 2007
Abstracts for paper and special sessions must be submitted online.
Special sessions may consist of embedded tutorials of one to two hours in length or may be focused on a specific topic with a list of invited papers/presentations relevant to that topic.
Panel proposals are due September 19, 2007
DVCon is looking for high energy creative panels. Proposals are due September 19.
To submit a panel idea, please submit an abstract and a list of panelist candidates via email to Kathy Embler at MP Associates at kathy@mpassociates.com.
Sponsored tutorials are due October 3, 2007
A limited number of sponsored tutorials will be also available. Proposals are due October 3. To submit sponsored tutorial ideas, please contact Kathy Embler at MP Associates at kathy@mpassociates.com. DVCon is sponsored by Accellera. Accellera is an industry consortium dedicated to the development and standardization of EDA languages, methods and formats, including design and verification languages.
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