Xilinx, Inc. (Nasdaq: XLNX) announced immediate availability of its 9.2 version of PlanAhead(TM) hierarchical design and analysis design tool. Offering a full speed grade advantage, this latest release of the company’s award winning product features expanded functionality of Xilinx(R) PinAhead technology. Released earlier this year, PinAhead technology provides FPGA designers with the ability to assign interface I/O groups to I/O pins simply by dragging into a graphical representation of the FPGA. PlanAhead 9.2 software further simplifies the complexities of managing the interface between the designer’s target FPGA and the PCB with the ability to import and export I/O port information through VHDL or Verilog headers.
The 9.2 release of the company’s award winning PlanAhead software also offers support for the company’s latest low-cost Spartan(TM)-3A DSP platform FPGA, the industry’s most cost-efficient devices optimized for wireless, video and consumer applications. With the latest 9.2 release, PlanAhead software now supports the entire line of Xilinx(R) Spartan(TM)-3 generation FPGAs.
“PlanAhead allows designers to divide a larger design up into smaller, more manageable blocks and focus efforts toward optimization of each module, improving performance and quality of the entire design,” said Salil Raje, Xilinx director for Design Planning and Verification. “Our latest 9.2 version allows designers to import and export I/O port information within their native HDL language, which further improves designer productivity.”
Improved Support for FPGA Pin Planning with PinAhead Technology
PinAhead technology facilitates early and intelligent pinout definition to eliminate many of the pinout related changes that typically happen downstream. Better user control of FPGA pinout early in the design process also offers significant improvements in performance, avoiding a non-optimal pinout which causes further delays when trying to meet timing requirements. By considering the data flow from PCB to FPGA die, optimal pinout configurations can be achieved quickly, thus reducing internal and external trace lengths and routing congestion.
During the pin planning process, PlanAhead 9.2 software allows users to better explore pinout information with extended reporting capabilities. PlanAhead 9.2 software can now display more information about the I/O ports assigned to individual I/O banks. Users can select an I/O Bank to view the values for VCCO, VREF, and I/O STANDARD. Users can also display the number of I/O Ports assigned to the I/O Bank and the number of remaining available pins for assignment. In addition, PlanAhead now provides an environment where users can better investigate individual clock regions by displaying information about the various I/O banks contained in each clock region. Users can also create their own port list with a GUI interface or import a comma separated values (CSV) spreadsheet. Through these multiple options, PlanAhead 9.2 software enables early decisions to be made, permitting PCB and FPGA designers to begin work much earlier with a much more realistic pinout configuration.
Xilinx PlanAhead design software streamlines the step between synthesis and place-and-route to give designers more control and insight into how designs are implemented to achieve their target Fmax with fewer design iterations. PlanAhead allows designers to utilize a block-based design methodology to minimize routing congestion, simplify clocking and interconnect complexity, and explore implementation options to avoid problems downstream.
Pricing and Availability
PlanAhead 9.2 software is available on all major operating systems as an option to the Xilinx(R) ISE(TM) design suite. Single-user licenses are currently available at a promotional price of at $2,495 US list.
Xilinx is the worldwide leader in complete programmable logic solutions.