Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, announced that CES Design Services, the Technology Center for Chip Design at Siemens IT Solutions and Services PSE, has deployed Cadence(R) assertion-based verification IP (ABVIP) to maximize quality and minimize completion time for its client designs and for its own standard IP blocks. The technology center, which serves both the Siemens group and non-Siemens customers, thoroughly evaluated Cadence’s assertion-based VIP and found that it works seamlessly with Incisive(R) Formal Verifier for formal analysis as well as with Incisive simulation. Even more importantly, Siemens found potentially damaging design flaws, and streamlined the early phases of verification using only logic designers to save months of development time.
Part of the Incisive Plan-to-Closure Methodology, Incisive assertion-based VIP maximizes project predictability and quality while minimizing resource consumption and verification environment bring-up time. Since ABVIP requires no stimulus or testbench, it enables verification to begin much earlier in the design cycle. Siemens achieved the earliest possible start and saw results most rapidly when the ABVIP was applied as the starting point for verifying modules under development. Cadence’s ABVIP supports the full set of Incisive verification engines, including simulation, formal analysis, and acceleration.
“Our exhaustive testing gave us high confidence in the assertion-based VIP from Cadence,” said Johann Notbauer, director of Chip Design at Siemens. “We easily integrated the ABVIP into our existing environment that was driven by design engineers unfamiliar with formal verification. The team was quite impressed and noted the significant new capabilities that included the ability to manage and view metrics based on the overall compliance of our design with AHB. This new capability enables us to deliver results much earlier and with increased schedule predictability.”
“We are excited to see that industry leaders such as Siemens appreciate the value of applying Incisive VIP, especially since doing so moves the verification process earlier in the design cycle and directly engages logic designers in verification,” said Steve Glaser, corporate vice president, Marketing, Verification Division at Cadence. “Assertion-based VIP, working in conjunction with formal analysis, is making life much easier for design teams by enabling them to improve design quality while completing the verification process sooner.”
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
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