Altera Corporation (NASDAQ: ALTR) announced the FPGA industry’s first full-compliance support for high-performance DDR3 memory interfaces. Under the newly ratified JESD79-3 JEDEC DDR3 SDRAM Standard, Altera’s Stratix(R) III family of FPGAs provides designers with the high-performance and low-power benefits of DDR3 memory that are becoming increasingly critical for a wide range of communications, computing and video processing applications.
These applications process large amounts of data that require quick and efficient access for optimum memory performance. Compliance with the JESD79-3 JEDEC DDR3 SDRAM standard meets the 1.5V, low-power supply voltage of DDR3 memory, which provides about a 30 percent system power reduction, faster performance and increased memory density for next-generation systems, while maintaining software compatibility with existing DDR applications.
Stratix III FPGAs support read and write leveling functionality embedded directly into the I/O element. This helps ensure compliance with the JEDEC write leveling requirement and corrects alignment of data reaching the FPGA fabric. DDR3 DRAM makers Elpida, Micron, Qimonda, Samsung and Hynix have all qualified various speed and density DDR3 memory devices for subsequent end-product use.
“By understanding our customers’ future design needs, and working closely with the JEDEC standards committee, we made sure Stratix III FPGAs include both read and write leveling functionality for DDR3 compliance,” said Richard Cliff, vice president of Design Engineering at Altera. “Our customers will now be able to quickly take advantage of the performance improvements in DDR3.”
The fly-by termination used in DDR3 improves signal integrity, but causes flight time skew between the clock and data signals. Altera’s implementation compensates for the skew by providing staggered DQ signals for high-speed operation.
DDR3 memory meets the low-power and high-performance requirements of today’s advanced memory applications. Stratix III FPGAs offer support for the DDR3 SDRAM high-speed external memory interface on up to 1,104 user I/O pins arranged in 24 modular I/O banks with dedicated DQS logic on all I/O banks and 31 embedded registers per I/O for maximum DDR3 performance. Stratix III devices support DDR3 with a maximum clock speed of 400 MHz and maximum data rate of 800 Mbps.
Designs in development with Stratix III FPGAs use Quartus(R) II design software version 7.1 subscription edition available. Stratix III FPGAs will begin shipping in August.
The DDR3 SDRAM standard includes features, functionalities, AC and DC characteristics, packages and ball/signal assignments. This standard defines the minimum set of requirements for JEDEC-compliant 512 Mbits through 8 Gbits for x4, x8 and x16 DDR3 SDRAM devices. JEDEC is the leading developer of standards for the semiconductor industry. The DDR3 Standard (pdf), published last month, is available on the JEDEC website.
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