Reduce Power, Energy Consumption in Low-Power SOCs via ISA Extension

Tensilica, Inc., will present a live webcast, “Reduce Power and Energy Consumption in Low-Power SOCs Through ISA Extension,” highlighting the abilities of configurable processors and discussing three specific, detailed task examples (AES encryption, Viterbi decoding, and FFTs) that benefit from this design approach.

Main discussion points include:

  • Configured processor cores can reduce task energy consumption by more than 10x
  • Many types of tasks can be accelerated using processor configuration
  • Configured processor cores reduce manual RTL coding and verification in low-power applications
  • Buses are not the ideal choice for low-power, on-chip interblock communications

The presenter for the July 18th broadcast will be Steve Leibson, Technology Evangelist, Tensilica.

Tensilica, Inc., is the recognized leader in configurable processor technology and has leveraged that technology to become the leading supplier of licensable controllers and DSP cores for mobile audio and video applications. Tensilica offers the broadest line of controller, CPU, network, and specialty DSP processors on the market today – including full software toolchain and modeling support – in both an off-the-shelf format via the Diamond Standard Series cores and with full designer configurability with the Xtensa processor family. The modern design behind all of Tensilica’s processor cores provides semiconductor companies and system OEMs with the lowest power, smallest area solutions for high-volume products including mobile phones and other consumer electronics, networking and telecommunications equipment, and computer peripherals.

The live webcast will take place on Wednesday, July 18, at 11:00 a.m. P.T. Afterwards, it will be available on demand from the EDN archives.