Apache Design Solutions, the technology leader in power sign-off and complete silicon integrity platform solutions for system-on-chip (SoC), analog-intellectual property (IP), and system designs, announced that Taiwan Semiconductor Manufacturing Company (TSMC) Reference Flow 8.0 includes Apache’s:
- RedHawk-ALP for power integrity of switched memory and on-chip low drop-out (LDO) voltage regulators
- Sahara-PTE for thermal integrity including stacked chips
- Sentinel-CPM for IC-system power integrity
TSMC’s Reference Flow 8.0 features statistical timing analysis for intra-die variation, automated DFM hot-spot fixing and new dynamic low-power design methodologies. Reference Flow 8.0 is the latest generation of TSMC’s design methodology that increases yields, lowers risks and improves design margins.
“TSMC continues to lead the market with advanced process technologies and flows, and we are pleased to see TSMC expand the use of Apache’s product portfolio to address the growing needs of power and noise management,” said Andrew Yang, CEO of Apache. “The ongoing collaboration between Apache and TSMC benefits our mutual customers and allows us to address their power and noise challenges and increase yield.”
“TSMC has been collaborating with Apache for the past several years to deliver methodologies for advanced process technologies,” said Kuo Wu, deputy director of design service marketing at TSMC. “Apache provides tools for improving accuracy of power and noise reduction methodologies in Reference Flow 8.0 that address design challenges at 65nm and 45nm, including advanced leakage management design techniques, thermal impact on leakage and timing, and IC-system co-design.”
Managing leakage continues to be a challenge as designs move towards 45nm and below. To control leakage one of the techniques used is to apply MTCMOS or power-gating switches to memories. RedHawk-ALP delivers analysis of memory behavior during “on,” “off,” and “power-up” modes with the capacity required for handling large GDS-based custom macros. In addition, RedHawk-ALP provides accurate modeling of on-chip LDO voltage regulator circuits with true transient behavior for full-chip power and noise analysis.
At advanced technology nodes, thermal impact on silicon performance is also a key concern, especially for stacked chips. Sahara-PTE delivers integrated power-thermal-electrical analysis and optimization to provide accurate views of how temperature and temperature variation impacts the chips leakage, timing, EM, and IR/dynamic voltage drop.
From a system perspective, the ability to perform better noise budgeting and optimal package selection early in the design process is important for reducing cost and minimizing design risk. Sentinel-CPM provides compact, SPICE-accurate model of the full-chip power delivery network that can be used by the package and I/O designers to accurately and efficiently analyze the system power and signal integrity (SI) behavior including inductor/capacitor (LC) resonance.
About Apache Design Solutions
Apache delivers the leading power sign-off solution adopted by 80% of top IDMs, fabless semiconductor companies, and foundries, as well as complete platform solution for silicon integrity of SoC, analog-IP, and system designs. Apache’s innovative platform considers all sources of noise that impacts the design–such as power, signal, package / system I/O, substrate, and temperature—Apache’s silicon integrity platform enables designers of leading networking, wireless, communication, consumer, and semiconductor companies to detect, fix, and prevent design weaknesses that can result in reduced yield or failed silicon / system. Apache’s vendor-neutral solutions enable designers to adopt any industry-standard physical design flow and are in production use by over 40 customers worldwide.
Apache Design Solutions, NSPICE, RedHawk, PsiWinder, Sahara, Sentinel, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc.