Altos Design Automation Inc. announced that TSMC Reference Flow 8.0 includes Altos’ statistical timing model generator Variety(tm). Reference Flow 8.0 supports 45nm process technology and is the latest generation of TSMC’s design methodology intended to increase yields, lower risks and reduce design margins. The new flow includes support for the creation of libraries to enable statistical static timing analysis (SSTA).
The collaborative effort between TSMC and Altos involved the creation and validation of statistical timing models using TSMC’s standard cell library. The models created by Variety include intra-die (random) variation as well as global systematic variations. TSMC analyzed a large number of paths and all were found to have good correlation to the Monte Carlo results for both the mean path delay and the standard deviation (1 sigma).
“Altos is delighted to be included in TSMC Reference Flow 8.0,” said Jim McCanny, Altos CEO. “Our joint efforts with TSMC have helped ensure that characterization of statistical timing models can be achieved in reasonable time with very good accuracy. Our unique inside view method for modeling intra-die variation is especially key to unlocking the potential of statistical based digital design.”
“At the 45-nanometer processes, chip performance becomes more susceptible to both systematic and random parameter variations; consequently statistical models are needed to reduce padded margins and improve yield,” said Kuo Wu, deputy director of design services marketing at TSMC. “Altos’ Variety provides a way to transform TSMC’s device models into cell level models, creating the required bridge between the process and SSTA.”
TSMC Reference 8.0 Flow
Reference Flow 8.0 supports TSMC’s 45nm process technology with advanced standard cell, standard I/O and an SRAM compiler. Key features address new design challenges at 45nm, including statistical timing analysis for intra-die variation, automated DFM hot-spot fixing and new dynamic low-power design methodologies.
Variety creates statistical timing cell models that represent the non-linear impact of any number of systematic and random parameter variations. All library timing data is characterized for variation including delays, transitions, timing constraints and pin capacitances. Variety generates SSTA models for a number of commercial SSTA products from a single characterization run.
Altos Design Automation provides ultra-fast, fully-automated characterization technology for the creation of library views for timing, signal integrity and power analysis and optimization. Altos’ advanced modeling solutions are used by both corner-based and statistical-based design implementation flows to reduce time to market and improve yield. Privately held, Altos was founded in 2005 in Santa Clara, CA. Its corporate headquarters is at 4020 Moorpark Ave., Suite 100, San Jose, CA 95117. Telephone: (408) 980-8056.
Variety is a trademark of Altos Design Automation, Inc.