Renesas Technology Corp. announced the development of an extremely high-performance transistor technology with low-cost fabrication capability for microprocessors and SoC (system-on-a-chip) devices of the 45-nm (nanometer) generation and beyond. The new technology improves the performance of CMIS transistors with a proprietary Renesas-developed hybrid structure — an advanced technology that the company previously announced in December 2006. Renesas Technology described the new, enhanced hybrid structure and presented test data at the 2007 Symposium on VLSI Technology being held in Kyoto, Japan from June 12, 2007.
Like the previous technology, the new semiconductor manufacturing technology has a p-type transistor with a titanium nitride (TiN) metal gate and an n-type transistor with a conventional polysilicon gate. However, the new p-type transistor uses a 2-layer gate structure instead of a single-layer gate for better control of the threshold voltage. Also, the new hybrid structure applies strained-silicon manufacturing techniques to boost current drive capability. These innovations produce about a 20-percent performance improvement compared to the previous Renesas hybrid structure. Importantly, the new structure can be fabricated at low cost because it requires no major changes to the current-generation manufacturing process.
An experimental chip containing transistors with a 40-nm gate length has been fabricated. Data from tests performed on this chip have confirmed world top-level drive performance: 1,068 µA/µm for the n-type transistor and 555 µA/µm for the p-type transistor at a 1.2 V power supply voltage.
Lowering threshold voltage and increasing current drive capability
The first element of the newly developed chip fabrication technology is the new p-type transistor gate structure, which consists of two titanium nitride layers. A high-k layer, CVD-TiN layer, PVD-TiN layer, and polysilicon are stacked on a silicon substrate in that order. The PVD-TiN layer is denser than the CVD-TiN layer, so silicon diffusion into the CVD-TiN layer from the polysilicon electrode is suppressed, preventing property changes that would otherwise increase the threshold voltage. Better yet, the two TiN layers actually lower the transistor’s threshold voltage by approximately 100 mV, to a level appropriate to a low-leakage device.
The other element of the newly developed technology is the strained-silicon technique already widely used in cutting-edge semiconductor devices. The technique can be used in the Renesas hybrid-structure because the fabrication process of the structure’s CMIS transistors closely resembles the transistors of a conventional CMOS process. The strained-silicon technique improves the drive performance in two ways. It distorts a channel part, forming a path through which current flows. It also widens or narrows silicon lattice spacing, enabling electrons and holes to move more easily.
About Renesas Technology Corp.
Renesas Technology Corp. is one of the world’s leading semiconductor system solutions providers for mobile, automotive and PC/AV (Audio Visual) markets and the world’s No.1 supplier of microcontrollers. It is also a leading provider of LCD Driver ICs, Smart Card microcontrollers, RF-ICs, High Power Amplifiers, Mixed Signal ICs, System-on-Chip (SoC), System-in-Package (SiP) and more. Established in 2003 as a joint venture between Hitachi, Ltd. (TOKYO:6501)(NYSE:HIT) and Mitsubishi Electric Corporation (TOKYO:6503), Renesas Technology achieved consolidated revenue of 953 billion JPY in FY2006 (end of March 2007). Renesas Technology is based in Tokyo, Japan and has a global network of manufacturing, design and sales operations in around 20 countries with about 26,500 employees worldwide.