Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, and Taiwan Semiconductor Manufacturing Company, Ltd. (TSE: 2330, NYSE: TSM) announced the availability of the Cadence(R) QRC Extraction tool for parasitic extraction for TSMC’s 45-nanometer (nm) process technology. Cadence’s QRC Extraction is immediately available to designers building fast and complex 45nm designs.
The 45nm node presents typical advanced technology challenges including aggressive design rules, smaller SRAM cells and higher gate density. As process technology scales down to 45nm, manufacturing effects impact design for manufacturability considerations that need to be addressed by accurate extraction technology to ensure reliable designs.
TSMC has validated that QRC Extraction provides accurate handling of 45nm manufacturing effects. Cadence QRC Extraction supports designers in high-growth IC markets, such as consumer electronics, mobile devices, RFID, and wired/wireless networking systems. Designers who need highly accurate extraction for fast and complex wireless SoC and RF integrated circuits can now use the Cadence QRC Extraction tool with TSMC’s 45nm process technology.
“Cadence QRC Extraction is the industry’s first extraction solution that is designed for the new challenges introduced at 45nm, due to CMP and lithography processes along with the use of ultra-low-k materials. New electrical models development is necessary to accurately predict interconnect ICs silicon behavior and also to account for process variability at the 45nm process node,” said Dr. Rachid Salik, vice president of Research and Development at Cadence. “Cadence QRC Extraction delivers the most comprehensive parasitic extraction available for fast system on chips. We are excited to collaborate with TSMC to provide a silicon-accurate extraction solution.”
“Successful qualification of the Cadence QRC Extraction addresses the need for an accurate extraction technology that matches TSMC’s silicon results,” said Kuo Wu, deputy director of design service marketing at TSMC. “Cadence QRC Extraction achieves excellent silicon correlation between measured and extracted results.”
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry industry’s largest portfolio of process-proven libraries, IP, design tools and reference flows. The Company’s total managed capacity in 2006 exceeded seven million (8-inch equivalent) wafers, including capacity from two advanced 12-inch GigaFabs, four eight-inch fabs, one six-inch fab, as well as TSMC’s wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 65nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan.
Cadence is a registered trademark, and the Cadence logo is a trademark of Cadence Design Systems, Inc in the United States and other countries.