CLK Design Automation announced that has linked its Amber(TM) Analyzer, the industry’s first true threaded and incremental static timing and signal integrity (SI) analysis solution, to Verific Design Automation’s Hardware Description Language (HDL) Component Software.
Verific’s Verilog Netlist Parser, a netlist-only parser that bypasses the HDL’s parse-tree, is blazingly fast and handles any size netlist, a requirement specified by CLK Design Automation. It serves as the front-end to the Amber Analyzer and runs smoothly on 64-bit machines, another CLK Design Automation condition.
Amber Analyzer is the first static timing and signal integrity tool that is fully threaded — from reading designs, calculating delay and crosstalk, to generating reports. The Amber platform is fully incremental across all classes of analysis (timing, signal integrity, leakage) for any type of design change, such as cells swaps, netlist modifications, constraints, or parasitics.
“With next-generation tools such as Amber, only the best-in-class software like those from Verific will help us meet complex design challenges,” remarks Isadore Katz, president and chief executive officer of CLK Design Automation. “We found that the Verific HDL Component Software had the capacity and performance our customers require for their designs.”
Adds Michiel Ligthart, Verific’s chief operating officer: “CLK Design Automation is helping to make multi-core processing design a reality. It gives us great pleasure to be working with team that is giving new meaning to timing analysis.”
Verific demonstrates its HDL Component Software in Booth #3464 this week at the 44th Design Automation Conference (DAC) at the San Diego Convention Center in San Diego, Calif.
CLK Design Automation debuts the Amber Analyzer at DAC. Attendees can see the Amber product overview in Booth #5671 or email firstname.lastname@example.org to pre-arrange for a private demonstration.
About Verific Design Automation
Verific Design Automation was founded in 1999 by electronic design automation (EDA) industry veteran Rob Dekker. It develops and sells C++ source code-based SystemVerilog, Verilog and VHDL front ends — parsers, analyzers and elaborators — as well as a generic hierarchical netlist database for EDA applications. Verific’s technology has been licensed in many applications, combined shipping more than 45,000 end-user copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: email@example.com.