Synplicity, Xilinx Target Area, Power Reductions with 65nm FPGA

In their ongoing commitment to provide push button flows in 65-nanometer (nm) FPGA design, Synplicity, Inc. (NASDAQ: SYNP), a leading supplier of software for the design and verification of semiconductors, and Xilinx, Inc. (NASDAQ: XLNX), the world’s leading supplier of programmable logic solutions, announced an extension of their Ultra High-Capacity Joint Task Force activities to address area utilization and lowering power consumption.

For more than a year, both companies have worked closely to define and implement new solutions to maximize the quality of results and productivity for ultra high-density designs implemented in Xilinx 65-nm Virtex(TM)-5 FPGAs. The first deliverable of the Synplicity-Xilinx joint task force (announced May 2006) was the development of SmartCompile(TM) Technology, an incremental design flow that improves run times by up to 6X while maintaining exact design preservation of unchanged logic. This RTL to place-and-route flow supports incremental changes so designers who need to make small modifications to an FPGA don’t have to recompile the entire device.

The initial phase of the Ultra High-Capacity Joint Task Force focused on providing dramatic improvements in overall quality of results and run time and ensuring the stability of results when incremental changes are made to an FPGA design. Phase II of the task force takes this progress to the next step — area reduction and lowering power consumption at 65-nm and below.

The overall goal of the joint task force is to provide designers with near push-button results for ultra high-density designs along with the ability to complete multiple design iterations per day. In view of the wide variety of applications enabled by ultra high-capacity FPGAs, the joint task force will deliver multiple design flows and tools optimized to meet the unique design requirements of these devices.

“We are pleased with the results of the first phase of our joint task force for improved incremental design,” said Ken McElvain, chief technology officer, Synplicity, Inc. “As the joint task force progresses, we expect it to continue to evolve to further address FPGA-based design and verification challenges — area and power reduction being among the top concerns voiced by our customers.”

“We’re looking forward to working closely with Synplicity on Phase II in our mutual design collaboration,” commented Bruce Talley, vice president of software, Xilinx, Inc. “This joint task force brings together our respective technology and engineering strengths to solve difficult problems through a unified solution. Synplicity and Xilinx intend to continue delivering solutions and products that provide our mutual customers with tools that better optimize designs for area and power on Xilinx 65-nm FPGAs.”

About Xilinx
Xilinx is the worldwide leader in complete programmable logic solutions.

About Synplicity
Synplicity(R) Inc. (Nasdaq: SYNP) is a leading supplier of innovative software solutions that enable the rapid and effective design of Programmable Logic Devices (FPGAs, PLDs and CPLDs) that serve a wide range of communications, military/aerospace, consumer, semiconductor, computer, and other electronic systems markets. Synplicity’s tools provide outstanding performance, cost and time-to-market benefits by simplifying, improving and automating key design planning, logic synthesis, physical synthesis and verification functions for FPGA, FPGA-based ASIC verification, and DSP designers. Synplicity is the number one supplier of FPGA synthesis solutions and has been rated #1 in customer satisfaction since 2004 in EE Times’ Annual FPGA Customer Survey. Synplicity products support industry-standard design languages (VHDL and Verilog) and run on popular platforms. The company operates in over 20 facilities worldwide and is headquartered in Sunnyvale, California.

Synplicity is a registered trademark of Synplicity, Inc. Xilinx, Virtex and SmartCompile are trademarks and registered trademarks of Xilinx, Inc.