The Silicon Integration Initiative’s Open Modeling Coalition has finalized the Si2 Effective Current Source Modeling (ECSM) Statistical Extensions specification draft. The new specification will be released, after approval, as an Si2 standard after a 60-day patent exclusionary period completes. On release, the statistical version of ECSM will become available to the broad electronics industry, both users and EDA vendors alike, regardless of Si2 membership.
Continuing to build on the popular ECSM format for modeling timing, noise, and power, the addition of the statistical library format extensions makes the ECSM standard the most advanced open modeling format available. In July 2006 Cadence Design Systems (Nasdaq:CDNS), Magma(R) Design Automation Inc. (Nasdaq:LAVA) and Extreme DA, with support from ARM (LSE:ARM) (Nasdaq:ARMHY), Virage Logic Corporation (Nasdaq:VIRL), and Altos Design Automation, had announced their intention to work together to accelerate the creation of a standard statistical analysis library format under the Open Modeling Coalition to support next-generation, variation-aware integrated circuit (IC) analysis tools. Subsequent to that, in October 2006, a statistical library format was contributed to the OMC in response to a Request For Technology (RFT) issued by Si2. Additional work on the statistical extensions was provided by Intel, Freescale, and Sun Microsystems after the contribution was made to the OMC. This effort to rapidly converge on a single open-standard statistical modeling format will facilitate the deployment of innovative statistical analysis technologies and enables greater design tool interoperability.
“The OMC is working to provide open standards for statistical modeling formats for design tools,” said Timothy Ehrler, OMC chair and senior manager of CAD Global Infrastructure at AMD. “We again see the on-schedule delivery of another important phase of a library modeling system and standard resulting from this collaborative effort by EDA, IP, and IDM industry leaders.”
The ECSM statistical extensions accurately model the impact of process and environmental variation – a potentially performance depriving problem – which can negate many of the advantages of moving to process nodes at or below 65nm. Using a statistical approach to timing analysis allows designers to unlock the true potential of smaller process technologies by reducing the pessimism that can rob chip performance in traditional design methodologies. The key to this emerging statistical standard is that it uses sensitivities to process and environmental device parameters to holistically model variations around nominal operating points. The statistical format accurately accounts for global, within-the-die, and random variations. The net result – fewer analysis corners, increased chip performance, and better silicon.
“This newest extension to ECSM addresses a critical need of our leading-edge member companies to effectively and accurately model manufacturing process variations in design,” says Sumit DasGupta, sr. vice president of Si2. “This capability is essential for our customers to stay on-board the ITRS roadmap and capitalize on the features offered by the latest technology nodes.”
This new ECSM technology will be demonstrated at the Design Automation Conference, June 3-7, in San Diego, CA. Altos Design Automation (Booth #1260) will be demonstrating Varietytm which supports the statistical extensions in ECSM. Cadence (in the Si2 Booth #5362) will also be demonstrating ECSM technology as implemented in their tools.
“The major roadblocks to adoption of statistical timing are characterization performance and lack of a standard library format,” says Jim McCanny, CEO of Altos Design Automation, Inc. “Altos is committed to removing these bottlenecks with on-going support for Si2′s ECSM statistical library format.”
About the Open Modeling Coalition (OMC)
The OMC technical objectives are to define a consistent modeling and characterization environment in support of both static and dynamic library representations for improved integration and adoption of advanced library features and capabilities, such as statistical timing. The system will support delay modeling for library cells, macro-blocks and IP blocks, and provide increased accuracy to silicon for 90nm and 65nm technologies, while being extensible to future technology nodes. Member companies are: Advanced Micro Devices (NYSE:AMD), Altos Design Automation, ARM (Nasdaq:ARMHY), Cadence Design Systems (Nasdaq:CDNS), Extreme DA, Freescale (NYSE:FSL), IBM (NYSE:IBM), Intel (Nasdaq:INTC), LSI Logic (NYSE:LSI), Nangate A/S, NXP Semiconductors, Renesas Technology Corp., Silicon Navigator, ST Microelectronics (NYSE:STM), Sun Microsystems (Nasdaq:SUNW), and Virage Logic (Nasdaq:VIRL).
Si2 is an organization of industry-leading semiconductor, systems, EDA and manufacturing companies focused on improving the way integrated circuits are designed and manufactured in order to speed time-to market, reduce costs, and meet the challenges of sub-micron design. Si2 is uniquely positioned to enable collaboration through a strong implementation focus driven by its member companies. Si2 focuses on developing practical technology solutions to industry challenges. Si2 represents over 100 companies involved in all parts of the silicon supply chain throughout the world.