A pair of vexing SoC design issues – Power Gating Analysis (PGA), and Simultaneous Switching Noise (SSN) – are now being addressed by low-power leader Sequence Design’s CoolTime with automated analysis capabilities that enable faster, more accurate power signoff. The new PGA and SSN capabilities address critical design issues in low-power wireless and high-speed interface designs, such as DDR.
“Both PGA and SSN can severely impact large, densely packed designs,” said Vic Kulkarni, Sequence president and CEO. “Unfortunately, they are difficult to model and analyze, but with these new capabilities, CoolTime automates this process with unequaled accuracy.”
CoolTime offers a fast “what-if” PGA capability that enables users to rapidly determine switch turn-on sequence to control peak rush current and minimize wake-up time. Rush current analysis examines the peak current required by a gated block as it turns on, and calculates the impact of this current on the power grid to other active sections of the chip. Wake-up time analysis determines how long it takes for instances in the power-gated block to reach the nominal supply voltage and be function and timing ready. CoolTime’s PGA capability provides “what-if” rush current and wake-up time analysis results within an hour instead of the days consumed by conventional methods.
When multiple output drivers switch simultaneously, they induce a voltage drop in the chip/package power distribution. This simultaneous switching momentarily raises the ground voltage within the device relative to the system ground. This apparent shift in the ground potential to a non-zero value is known as SSN or ground bounce. Many designs in high-volume applications such as storage, computing, and communications are impacted by SSN, including those with high-speed parallel interfaces (DDR), highly inductive, or high-pin-density packaging.
Current manual SSN analysis methodologies are time-consuming, error prone, and capacity constrained, often requiring a week or more to obtain a correct simulation netlist. CoolTime now analyzes and determines SSN with enhanced designer productivity and increased silicon integrity through the use of accurate internal die parasitics assembled from extraction. It provides accurate on-chip parasitic extraction and automates the entire analysis, reducing the time to prepare the netlist from a week to an hour. For the user-defined region of the pad ring, it generates chip parasitics, applies parasitic reduction, determines IO instances in the region, sensitizes IO instance pins, stitches all SPICE components (including package model), and loads results in CoolTime’s waveform viewer.
These improvements minimize manual setup and human error, reduce debug and simulation setup time, and provide fast netlist generation for multiple IO regions.
About Cool Products
Sequence’s Cool Products family – CoolTime, CoolPower, and CoolCheck – cut design closure times by preventing time-consuming iterations between separate timing, SI, power analysis and optimization tools.
CoolTime, the industry’s most accurate dynamic voltage drop analysis and optimization solution, concurrently analyzes timing, signal integrity, static IR drop, and electromigration. CoolPower includes automated power, timing, and signal integrity optimization features. Both leakage and dynamic power can be automatically optimized using CoolPower’s multi-Vt cell swapping and cell resizing, and its MTCMOS power gating optimization slashes leakage power up to 100X or more. CoolCheck enables effective power grid debug early in the flow with a fast vectorless technique for finding high resistive connectivity of standard cells and macros.
Sequence Design accelerates the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence Design-For-Power solutions give customers the competitive advantage necessary to excel in aggressive technology markets.