Lattice Adds Support for HyperTransport, Memory Interfaces

Lattice Semiconductor Corporation (NASDAQ: LSCC) announced industry-leading FPGA support and performance for HyperTransport(TM) technology and three popular memory interfaces. The LatticeSC(TM) and LatticeSCM(TM) FPGA families (collectively, the “LatticeSC/M” families) now support HyperTransport technology at rates up to 1600Mbps, QDRII+ rates up to 750Mbps, RLDRAM(R) II rates of 800Mbps and DDR2 interface speeds of 667Mbps. HyperTransport technology and the memory interfaces are implemented using the LatticeSC/M families’ innovative PURESPEED(TM) I/O technology. The memory controller IP (intellectual property) is implemented in Lattice’s unique and low power Masked Array for Cost Optimization (MACO(TM)) structured ASIC technology.

“We are pleased to announce these IP cores and device characterization results, ” said Stan Kopec, Lattice corporate vice president of marketing.” Our HyperTransport technology interface operates twice as fast as competitive claims, including those for next generation parts.”

“Lattice Semiconductor has achieved an impressive milestone with these results,” said Randy Allen, corporate vice president & general manager, Server/Workstation Division, AMD. “The company’s support of HyperTransport technology and participation in the AMD Torrenza initiative helps further our ecosystem and contributes to the role FPGAs play in application specific co-processing subsystems for AMD64 technology.”

“We are pleased to work with Lattice Semiconductor to create an infrastructure for next generation architectures requiring ultra-dense, high-performance memory sub-systems,” said Raymond Fontayne, Segment Marketing Manager at Micron Technology, Inc. “The Lattice high- performance MACO memory controller IP is ideal for interfacing to our low power DDR2 and high-performance, low latency RLDRAM memory solutions. Customers can quickly develop platforms in multiple market applications, including networking and computing.”

Lattice’s unique MACO embedded structured ASIC blocks are available on LatticeSCM FPGA devices and deliver pre-engineered, standard-compliant IP functions developed by Lattice to shorten end-system time to market. The enhanced DDR, RLDRAM and QDR memory controllers also are available on the LatticeSC/M family of FPGAs, and are supported by Lattice’s next generation of design tools, the recently announced ispLEVER(R) version 7.0 software design tool suite. There is no IP fee associated with the use of any pre-engineered, MACO-based IP core.

Multi-Bit LVDS I/O Reference Design Now Available
Lattice also is announcing the availability of the PURESPEED I/O Alignment Reference Design. This reference design demonstrates the power of the LatticeSC/M families’ patented Adaptive Input Logic block that delivers data rates of up to 2 Gigabits per second. AIL is designed to continuously monitor and dynamically adjust the clock/data relationship on a bit by bit basis with a resolution down to 40 picoseconds. This ability is critical for customers who want to build large, high-speed data pipes out of multiple smaller ones. In the reference design, data is sent across mismatched trace lengths to introduce different amounts of skew. A word alignment block, together with AIL, is used to realign this skewed data bus. This powerful realignment capability is readily observed on an oscilloscope as part of the reference design.

AIL is one of the key building blocks within the PURESPEED I/O architecture featured on the LatticeSC/M family of FPGAs. Other key components of the PURESPEED I/O include:

  • Powerful buffers with dedicated I/O logic to provide seamless and robust parallel source synchronous I/O solutions
  • Highly flexible built-in shift register and DDR/SDR Mux/Demux logic
  • Dedicated Clock Divider circuitry for by-2 and by-4 clock division

This reference design is now available and can be downloaded for free.

About Lattice Semiconductor
Lattice Semiconductor Corporation provides the industry’s broadest range of Programmable Logic Devices (PLD), including Field Programmable Gate Arrays (FPGA), Complex Programmable Logic Devices (CPLD), Mixed-Signal Power Management and Clock Generation Devices, and industry-leading SERDES products. Lattice continues to deliver “More of the Best” to its customers with comprehensive solutions for system design, including an unequaled portfolio of high-performance, non-volatile and low-cost FPGAs. Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets.

Lattice Semiconductor Corporation, Lattice (& design), L (& design), LatticeSC, LatticeSCM, PURESPEED, ispLEVER, MACO and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. AMD, the AMD Arrow logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. HyperTransport and HTX are licensed trademarks of the HyperTransport Technology Consortium. Micron and the Micron orbit logo are trademarks of Micron Technology, Inc. RLDRAM is a trademark of Infineon Technologies AG in various countries, and is used by Micron Technology, Inc. under license from Infineon.