Calypto to Demonstrate Power Optimization, Verification Tools at DAC

Calypto(TM), the leader in sequential analysis technology, will demonstrate its SLEC(TM) (Sequential Logic Equivalence Checking) and PowerPro(TM) CG (Clock Gating) during the 44th Design Automation Conference (DAC) in booth #2680. DAC will be held June 4-7 at the San Diego Convention Center in San Diego, Calif.

Additionally, Calypto’s Chief Architect Anmol Mathur will present a paper titled, “Design for Verification at System-Level and RTL,” during a special session on Functional Verification of ESL Models to be held Tuesday, June 5, from 4:30-6:30 p.m.

SLEC is a Sequential Logic Equivalence Checker that verifies register transfer level (RTL) designs, providing efficient bug finding without writing testbenches or assertions. SLEC System is used in electronic system level (ESL) design flows to verify that RTL implementations matches system-level models written in C/C++ or System C. SLEC RTL verifies RTL power and performance optimizations. Unlike combinational logic equivalence checking tools, SLEC can verify sequential design changes such as clock gating and retiming.

Recently announced PowerPro CG, an automated RTL power optimization solution, works at RTL and above where there is greater power savings. It dramatically reduces power with little or no impact on timing or area, and has reduced power by up to 60% on initial customer designs. Unlike power optimization tools working at the gate level, PowerPro CG identifies clock-gating opportunities using sequential analysis of the RTL code.

About Calypto
Founded in 2002, Calypto Design Systems, Inc. enables SoC design teams to bridge System and RTL for semiconductor design, saving millions of dollars in design costs and silicon re-spins. It delivers software products to leading edge semiconductor and systems companies worldwide. Calypto is privately held with venture funding from Cipio Partners, JAFCO Ventures, Tallwood Venture Capital and Walden International. It is a member of the Cadence Connections program, the IEEE-SA, Synopsys SystemVerilog Catalyst Program and the Mentor Graphics OpenDoor program. Corporate Headquarters is located at: 2933 Bunker Hill Lane, Suite 202, Santa Clara, Calif. 95054. Telephone: (408) 850-2300. Email:

Calypto, PowerPro and SLEC are trademarks of Calypto Design Systems Inc.