Sierra Targets 45nm Physical Design with New Technologies

Sierra Design Automation(TM), Inc., the technology leader in place-and-route solutions, announced the availability of several innovations to Sierra’s place and route (P&R) platform. These capabilities address critical 45nm design challenges including interconnect resistance variation, complex design rule checks (DRCs) and yield. The new technologies are built on Sierra’s proven variability-driven physical design platform – the only solution that can comprehensively handle variations in design modes, process corners, and lithography. These capabilities are targeted at high-end customers in different market segments such as wireless, handheld, graphics, set-top boxes, networking and processors.

The scaling of process technology into 45nm regime is characterized by a significant increase in interconnect resistance. The resistance of interconnect is one of the integral 45nm implementation challenges due to its impact on circuit performance and reliability of clock trees. Engines such as placement, CTS and routing need to optimize for increased resistance and large variation of resistance across different process corners by optimally trading-off circuit performance, power consumption, and die size. Traditionally, techniques such as buffering were used to address RC problems in earlier nodes. But at 45nm, such techniques break down, resulting in over-buffering causing increased power consumption and die-size. A dynamic tradeoff between buffering the wire versus assigning it to less resistive layers is essential in order to achieve the best delay/area trade-off.

45nm also brings with it increased complexity in routing design rules and design for manufacturability (DFM) requirements for an increased yield. Conventional routing approaches which rely on extensive post-processing to address complex design rules and DFM metrics will no longer work at 45nm. These rules have to be modeled much earlier in the routing flow in order to achieve DRC cleanliness and higher DFM scores.

Sierra delivers the following key technologies to address the 45nm requirements:

1) The FalconGR global routing technology assigns layers dynamically throughout the P&R flow and is embedded within every engine such as placement, CTS and detailed routing. The FalconGR routing technology ensures that resistive critical wires are assigned to layers with the least resistance and achieves an optimal delay/area tradeoff. This prevents over-buffering of the circuit and achieves the best performance.

2) The Multi-Corner CTS technology automatically minimizes intra- and inter-corner skew and insertion delays in a single run. Large resistance variations across process corners are seamlessly handled resulting in a clock tree implementation that works across all the process corners. This requires a dynamic measurement of cell and wire delays in the clock tree across different process corners concurrently during clock tree construction.

3) The global, track and detailed routing engines have been enhanced to model complex 45nm design rules and recommended DFM rules throughout the routing flow, which eliminates the need for expensive post-processing to achieve DRC and DFM closure. Advanced techniques such as via optimization, “liquid” wire spreading and a customizable DRC rule interface enables designers to achieve higher DFM scores.

These technologies, in conjunction with Sierra’s unique variation and litho-driven design closure implementation system deliver the most comprehensive P&R solution for 45nm and below. Since its announcement last year, Sierra’s Olympus-SoC P&R platform has been actively adopted by high-end customers looking for a next-generation physical design solution to implement 65nm and 45nm designs.

“NEC Electronics uses cutting-edge design tools and methodologies to design some of the most advanced chips in its proven EMMA platform, which delivers the highest quality MPEG signal processing technology for digital AV applications such as set top boxes, digital TVs, and DVD recorders,” said Masao Hirasawa, General Manager, Digital Consumer LSI Division, NEC Electronics. “We evaluated Sierra’s Olympus-SoC router on DRC readiness, routing quality and manufacturing related design closure features for our advanced processes, and are very impressed with the overall quality of results. We look forward to working closely with Sierra to adopt it in our methodology.”

“STMicroelectronics continues to pioneer the design of complex ICs for demanding applications such as set-top boxes, secure smart cards and mobile multimedia,” said Francois Remond, CAD & design methodology director, Home Entertainment & Displays Group, STMicroelectronics. “Sierra’s design-for-variability (DFV) solution is already an integral part of our flow and is proven with multiple tapeouts. With Olympus-SoC’s deployment, we have extended the usage all the way to routing for our advanced technologies. We are impressed with the DRC cleanliness, timing and litho-driven routing, and with the overall design closure capabilities.”

“Our customers are designing some of the most challenging chips across various application segments in advanced process nodes such as 65nm and 45nm” said Pravin Madhani, president and CEO, Sierra Design Automation, Inc. “Sierra’s next generation place & route solution, Olympus-SoC, addresses the physical design and manufacturing challenges at these nodes comprehensively and delivers a significant time-to-market advantage with exceptional quality of results. Transition to 65nm and 45nm is a disruptive event and we are seeing widespread adoption of the Sierra solution at these nodes.”

About Sierra Design Automation and Sierra Olympus-SoC
Sierra Design Automation’s world-class electronic design automation (EDA) team is focused on providing semiconductor designers with innovative integrated circuit (IC) and system-on-chip (SoC) implementation solutions that comprehensively address the performance, capacity, time-to-market, and variability challenges occurring at the 65nm, 45nm, and smaller process nodes. Olympus-SoC(TM), Sierra’s flagship product, provides the next generation place and route system that concurrently addresses variations in lithography, process corners and design modes. It is built on Sierra’s design for variability technology, Sierra Pinnacle(TM), the customer-proven and industry leading physical implementation solution. Technology highlights include lithography-driven detailed router, embedded signoff quality timing engine, adaptive variability engine in addition to an open architecture and ultra-compact database that can handle extremely large capacities. Sierra is a privately funded EDA company founded in January 2003.

Sierra Design Automation, Sierra Pinnacle, and Sierra Olympus-SoC are trademarks of Sierra Design Automation, Inc.