Sequence Design announced upgrades for its Columbus parasitic extractors, aimed at high-frequency design, 65nm characterization, and analysis of simultaneous switching noise (SSN). These new features cap a line of related improvements over the past year, including Statistically Accurate Corners for 65nm interconnect, Speedview-AMS for full-custom voltage-drop and EM analysis, and Fast Rail extraction for LVS flows.
Columbus-AMS has modeled frequency-dependent inductance since it pioneered RLC extraction in 1999. For designs handling 10GHz signals, it now adds frequency-dependent resistance as part of inductance modeling. Users can still simulate efficiently, because this option does not increase network size or limit Columbus’s RLC parasitic reduction.
Flip-chip designs often include 45-degree segments connecting solder bumps to their pads. For analyzing rails and I/O signals in flip-chip designs, Columbus-Turbo now produces compact models of 45-degree net segments. Similarly, Columbus-AMS can produce RLC models for 45-degree segments for nets connecting PCI-X, SATA, and other high-frequency I/Os.
The Columbus family now supports Pextra Corporation’s CapSe field solver. Users can now build process libraries 5X faster than previous-generation field solving, without reducing Columbus-AMS’s best-in-class accuracy or requiring any changes in how you use the Columbus extractors.
Columbus-AMS recently added Statistically Accurate Corners (SAC). SAC eliminates unrealistic pessimism due to 65nm interconnect variation, which can impose 30% timing penalties in designs.
Columbus now allows users to combine SAC with temperature variations for analyzing full PVT variations. These PVT corners work with existing STAs, instead of requiring a complex transition to statistical STA tools.
Independent of SAC, Columbus-AMS can now extract up to 5 PVT combinations simultaneously. Simultaneous extraction runs 2.5X faster than extracting 5 PVT points separately.
Speedview-AMS provides efficient graphical analysis of power rails in full-custom designs. Now supporting Columbus-Turbo for Fast Rail extraction and Columbus-AMS for signal nets, Speedview-AMS eliminates the bottlenecks in the rail-extraction flow, allowing users to concentrate on simulating and analyzing voltage-drop and electromigration in their designs.
The Columbus extraction product family is part of Sequence’s high-performance, low-power design lineup: PowerTheater, CoolPower, CoolCheck, and CoolTime. Columbus-AMS is both a foundation for the company’s RTL-to-silicon, power-aware design tools for SoCs and the industry’s leading RLC parasitic extraction tool for high-performance digital and analog/mixed-signal designs. Sequence customers have taped out over 200 successful, high-performance designs using Columbus-AMS extraction.
Information and registration information on DAC demos for Sequence’s entire line of award-winning extraction products is available online.
Sequence Design accelerates the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence Design-For-Power solutions give customers the competitive advantage necessary to excel in aggressive technology markets.