Lattice Semiconductor Corporation (NASDAQ: LSCC) announced major performance and functional enhancements in Version 7.0 of its ispLEVER(R) FPGA design tools. Optimized logic synthesis, map, and place-and-route algorithms have boosted Lattice FPGA performance demonstrably by 12% on average, with certain large, system-level benchmark circuits benefiting by an over 40% improvement, compared to the previous ispLEVER release. Tool performance has also been substantially improved, dramatically reducing design fit runtime and workstation memory requirements. In addition, the ispLEVER 7.0 software features Reveal(TM), Lattice’s second generation logic analysis / hardware debug tool, a more accurate and user friendly Power Calculator module and a variety of enhancements to the LatticeMico32(TM) embedded open source microprocessor design tools. Full support for the newly announced LatticeXP2(TM) 90nm non-volatile FPGA device family has been added to Lattice’s ever growing portfolio of supported architectures.
“The technical innovations we are delivering in ispLEVER 7.0 take full advantage of Lattice’s powerful silicon,” said Chris Fanning, Lattice corporate vice president, Enterprise Solutions. “Customers have complimented us on the ease-of-use of our ispLEVER tools. Now we’ve added best-in-class performance while reducing runtime and system hardware requirements. This increased productivity sets a new standard for FPGA design.”
FPGA Performance Improvements
FPGA performance has increased by up to 46% for system-level FPGA benchmark designs requiring >50K LUTs, averaging 12% across a wide range of typical design benchmarks and densities of Lattice FPGAs. In addition, for large FPGA designs where runtime is most critical, Lattice’s ispLEVER 7.0 software has reduced design compile times by more than 70%, with an average improvement of approximately 30% faster. Finally, the amount of workstation RAM required to successfully complete large, densely packed designs has also been reduced by almost 40%, allowing PC-based design fitting for larger LatticeSC(TM) FPGA designs.
New Features in ispLEVER 7.0
A host of new features make ispLEVER 7.0 easier to use and enhance user productivity. Major new features include:
Reveal Logic Analyzer: Designed to support the FPGA designer’s intuitive design debug process, the Reveal logic analyzer uses a signal-centric model for embedded logic debug. The user first defines signals of interest and the Reveal tool then inserts the instrumentation (added FPGA test / monitoring circuitry) along with the proper connections to enable the required observations. The ability to specify complex, multi-event triggering sequences, a feature not offered in any other FPGA vendor’s logic analyzer, makes system-level design debug smoother and faster.
The ispLEVER Power Calculator has been enhanced with a new environment-aware power model, new graphical power displays and a variety of useful reports. New thermal resistance options model real world thermal conditions, including heatsinks, airflow, and the printed circuit board complexity, while graphical power curves illustrate operating temperature profiles.
LatticeMico32 soft microprocessor system design, now supporting the LatticeXP2 family, includes new features as well. Code tracing allows the user to view and debug code leading up to a specified breakpoint, an optimized C library has been added to reduce the size of the code and new DDR, Serial SPI Flash and SDRAM Wishbone interface peripherals have been added to complete system-on-a-chip FPGA designs.
ispLEVER Pro and Classic
In addition to the standard Lattice ispLEVER package, Lattice is also offering a new optional package called ispLEVER Pro concurrent with Version 7.0 that includes a suite of commonly used, high value IP cores bundled with the software. This IP suite includes DDR, DDR2, FIR Filter, FFT and Tri-Speed MAC modules supporting multiple Lattice FPGA families, and allows users to complete an unlimited number of FPGA designs using any number of these cores during the license period.
Lattice also includes its ispLEVER Classic software with all ispLEVER shipments. ispLEVER Classic supports all mature Lattice programmable logic families including its popular SPLD, CPLD, ispGDX(R), ispGDX2(TM), ispXPGA(R) and ORCA(R) product families.
Lattice’s ispLEVER 7.0 for Windows, LINUX and UNIX users is available immediately starting at a price of $895 for the Windows PC version. The annual, node-locked license for ispLEVER PRO, supporting an unlimited number of IP-based FPGA designs, carries an attractive $1495 list price.
About Lattice Semiconductor
Lattice Semiconductor Corporation provides the industry’s broadest range of Programmable Logic Devices (PLD), including Field Programmable Gate Arrays (FPGA), Complex Programmable Logic Devices (CPLD), Mixed-Signal Power Management and Clock Generation Devices, and industry-leading SERDES products. Lattice continues to deliver “More of the Best” to its customers with comprehensive solutions for system design, including an unequaled portfolio of high-performance, non-volatile and low-cost FPGAs. Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets.
Lattice Semiconductor Corporation, Lattice (& design), L (& design), ispGDX, ispGDX2, ispLEVER, ispXPGA, ORCA, Reveal, LatticeSC, LatticeXP2, LatticeMico32 and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.