Bluespec to Demonstrate Synthesizable Testbench at DAC

Bluespec(TM) Inc. will demonstrate a hardware/software co-emulation environment running on EVE’s ZeBu hardware-assisted verification platform in Booth #6963 during the 44th Design Automation Conference (DAC). DAC runs June 4-7 at the San Diego Convention Center in San Diego, Calif.

Developer of electronic system level (ESL) synthesis for control logic and complex datapaths in chip design, Bluespec’s hardware demo, freed from the constraints of synthesizable RTL subsets, will show an AzureIP(TM) Foundation Library-based implementation including hardware transactors, a synthesizable testbench and AXI(R) bus components integrated with ZeBu.

An additional highlight will be a demonstration of a field programmable gate array (FPGA) implementation of an H.264 video decoder designed in nine months with half the lines of code of a pure, non-hardware C-based implementation.

Also on display will be BluDACu, a parameterized hardware implementation of Sudoku running with a software graphical user interface (GUI) front end.

And, Rishiyur Nikhil, Bluespec’s chief technical officer, will participate on a panel titled, “TLM: Crossing Over from Buzz to Adoption,” June 6 from 10:30 a.m.-noon.

The ZeBu-based demonstration follows two recent announcements. The first introduced Bluespec’s AzureIP bus fabric library components. The second announced an integrated solution of ESL synthesizeable transactors and models that run on EVE’s ZeBu. The link between ESL synthesis and ZeBu offers high simulation speed with hardware accuracy early in the development cycle for architectural exploration, virtual prototyping, modeling and verification. The result is a single development environment for models, transactors, implementations and synthesizable verification testbenches, and a rich foundation library of intellectual property (IP).

About Bluespec
Bluespec Inc. manufactures industry standards-based Electronic Design Automation (EDA) toolsets that significantly raise the level of abstraction for hardware design while retaining the ability to automatically synthesize high-quality RTL, without compromising speed, power or area. The toolsets, the only ones focused on control and complex datapaths, allow ASIC and FPGA designers to reduce design time, bugs and re-spins that contribute to product delays and escalating costs. More information can be found by calling (781) 250-2200.

Bluespec and AzureIP are trademarks of Bluespec Inc.