Synplicity to Demonstrate ASIC, ASSP Verification at DAC

Synplicity, Inc. (Nasdaq:SYNP), a leading supplier of software for the design and verification of semiconductors, will underscore the company’s commitment to the fast growing, high-performance ASIC/ASSP verification and FPGA-based prototyping market at this year’s Design Automation Conference (DAC) in San Diego, June 4 through June 8.

Industry Panel—ASIC Verification
Of particular interest to ASIC/ASSP users will be a panel on how industry and customers are addressing today and tomorrow’s
verification challenges. Moderated by Gary Smith, the industry’s preeminent EDA analyst, the event will feature panelists from HARDI Electronics, prototyping users, Synplicity and Synopsys.

Despite new verification methodologies, such as assertion-based verification, random-constraint verification, dynamic formal verification, etc., designer productivity continues to depend on the raw performance of verification tools. At the implementation level, the highest performance is provided by FPGA-based prototypes. Until now, such prototypes lacked a productive and elegant software environment to allow users to take advantage of this speed. Thus, there’s a productivity gap.

Industry panelists will debate and offer insight on how, and if, FPGA-based prototyping will need to evolve to solve the rising verification crisis. More importantly, will FPGA-based prototyping emerge as THE standard for high-performance verification?

DAC Verification Demonstrations (and more)
Complementing Synplicity’s industry panel on ASIC verification will be a host of product demonstrations that not only highlight the company’s focus on the ASIC verification market, but also its best-of-breed tools and technologies.

Products being demonstrated in Synplicity’s booth include:

  • ASIC Verification
    • Multi-chip Solutions

      • yIdentify Pro with TotalRecall Technology, Full Visibility Functional Verification
      • yCertify Multi-FPGA Partitioning Solution
    • Single-chip Solutions
      • yIdentify Pro with TotalRecall, Full Visibility Functional Verification
      • ySynplify Premier Single-FPGA Prototyping Environment
  • FPGA Implementation
    • Synplify Premier FPGA Implementation and Debug
    • Identify RTL Debugger
    • Identify Pro Full Visibility Functional Verification
  • DSP Synthesis
    • Synplify DSP, DSP Synthesis for FPGA Designers
    • Synplify DSP ASIC Edition, DSP Synthesis for ASIC Designers

The Synplicity-sponsored ASIC Verification panel will be held Tuesday, June 5, from 7:30 a.m. to 8:15 a.m. in room 32AB of the San Diego Convention Center. A Continental breakfast will be provided beginning at 7:00 a.m.

Product demonstrations will be available during exhibit hours at DAC, June 4 – 7, in Synplicity’s booth, # 4278, at the San Diego Convention Center.