Apache Design to Hold Dynamic Power, Clock Jitter Tutorials at DAC

Apache Design Solutions, the leader in power signoff and complete silicon integrity platform solutions for system-on-chip (SoC), analog intellectual property (IP), and system designs, announced that they will be holding free technical tutorials at the design automation conference (DAC) in San Diego, California. In these tutorials, the customers will gain hands-on experience by running Apache’s RedHawk for dynamic power analysis and optimization and PsiWinder for full-chip clock jitter analysis and timing margin management.

RedHawk Tutorial
Tuesday, June 5, 2007 at 2:00 PM – 3:30 PM
Free technical tutorial including hands-on experience on dynamic power analysis and optimization from early design to signoff using RedHawk.

PsiWinder Tutorial
Monday, June 4, 2007 at 2:00 PM – 3:30 PM
Wednesday, June 6, 2007 at 2:00 PM – 3:30 PM
Free technical tutorial including hands-on experience on full-chip clock jitter analysis in the presence of crosstalk and power noise using PsiWinder.

Apache Booth #6382
Design Automation Conference
San Diego Convention Center, San Diego, CA

About Apache Design Solutions
Apache delivers the leading power sign-off solution adopted by 80% of top IDM, fabless semiconductor, and foundries and a complete platform solution for silicon integrity of SoC, analog IP, and system designs. Apache’s innovative platform considers all sources of noise that impacts the design—such as power, signal, package / system IO, substrate, and temperature—Apache’s silicon integrity platform enables designers of leading networking, wireless, communication, consumer, and semiconductor companies to detect, fix, and prevent design weaknesses that can result in reduced yield and failed silicon or system. Apache’s vendor-neutral solutions enable designers to adopt any industry-standard physical design flow and are certified by TSMC’s Reference Flows (NYSE:TSM).