Zuken, Aldec Offer Design and Verification Flow for FPGA

Adopting programmable devices is set to become significantly easier as a result of a partnership between Zuken, the engineering consulting company, and Aldec, the HDL verification specialists. By combining Zuken’s expertise in system- and board-level electronics design and verification with Aldec’s mixed HDL verification technology, the two companies will be able to offer a combined design and verification flow for flexible field programmable gate array (FPGA) devices on printed circuit boards (PCBs). At this time, the partnership will focus integration efforts on Zuken’s enterprise-wide PCB design suite, CR-5000.

The increased density, higher performance and flexibility of FPGA devices has driven a growth in their market share over that of ASICs in recent years. But the versatility and huge gate count of the latest FPGAs introduces design challenges associated with library management, data sharing, revision control and mixed VHDL, Verilog, SystemC and SystemVerilog simulation; demanding that the complete PCB and FPGA design and verification process be harmonized.

CR-5000 Integration
Initial development will allow designers to launch Aldec’s mixed language simulation technology from within CR-5000 System Designer for access to project-specific design data. It will be possible to perform FPGA timing simulation for the complete design rather than for the individual FPGAs in isolation. Additionally, within CR-5000 Board Designer, layout engineers will be able to perform pin swaps that will concurrently update all PCB and FPGA design data, rather than only be able to perform this on request from the FPGA implementation engineer.

DAC 2007
Zuken and Aldec are now accepting appointments for product demonstrations and partnership roadmap discussions at DAC 2007, in San Diego, California USA – June 4 – 7.

About Zuken
With over 30 years experience, Zuken has grown to become the world’s leading provider of EDA software and electronic product lifecycle management (e-PLM). With headquarters in Japan and listed on Level 1 of the Tokyo Stock Exchange, development and support centers are located in 10 countries – including the US, Germany, UK, France, Italy, China and Taiwan.

About Aldec
Aldec, Inc., established in 1984, is committed to delivering high-performance, HDL-based design verification software for Unix, Linux, and Windows platforms.