The Silicon Integration Initiative (Si2) announced two workshops being hosted at the Design Automation Conference (DAC) show to be held at the San Diego Convention Center in San Diego, from June 3-7, 2007. The “Low Power Coalition Workshop – Standards for Low Power Design Intent” will be held on June 3, from 12:30PM – 3:30PM in Room 6D. The “3rd Integrated Design Systems Workshop: Models for Design and Manufacturing – How Modeling Challenges are Touching Every Aspect of IC Design” will be held on June 4, from 12PM – 5PM in Room 6A, and includes lunch. Following are summaries for each workshop.
Low Power Coalition Workshop – Standards for Low Power Design Intent
Low-power requirements are a primary concern for IC designs across all product categories. They affect all electronic systems, all of which are experiencing intense pressure to reduce power consumption. For the IC design process, several advanced techniques have emerged to reduce power consumption in SoCs including the use of multiple power domains, multiple supply voltages, dynamic and adaptive voltage and frequency scaling, and task-dependent power shut-off. However, these new techniques impose new requirements on existing design libraries, tools and methodologies. The Low Power Coalition is developing new approaches to help specify, manage and communicate power-related information and constraints consistently throughout the design flow. One of the first actions of the LPC was the issuance of the Common Power Format specification. CPF captures low power design intent so that it can be used to consistently communicate low power constraints throughout the IC design flow. This workshop will cover some of the recent activity and planned roadmap of the LPC.
3rd Integrated Design Systems Workshop: Models for Design and Manufacturing – How Modeling Challenges are Touching Every Aspect of IC Design
Rules-based design methods are rapidly being replaced by the need for models representing everything in modern chip design flows — from the system-level analysis through foundry process variation. This workshop will bring together experts in important modeling areas such as: delay calculation, statistical timing, low power, DFM, yield, IP blocks, and pcells.
Si2 is an organization of industry-leading semiconductor, systems, EDA and manufacturing companies focused on improving the way integrated circuits are designed and manufactured in order to speed time-to market, reduce costs, and meet the challenges of sub-micron design. Si2 is uniquely positioned to enable collaboration through a strong implementation focus driven by its member companies. Si2 focuses on developing practical technology solutions to industry challenges. Si2 represents over 100 companies involved in all parts of the silicon supply chain throughout the world.