Verific Design Automation announced that innovative design for test (DFT) software provider DeFacTo Technologies has selected its hardware description level (HDL) Component Software to serve as the register transfer level (RTL) front end for its scan insertion software to be introduced later in the year.
DeFacTo’s software, meant to enhance the DFT process and increase the testability of integrated circuits (ICs) and systems on chip (SoCs), utilizes both static and RTL elaboration, operating simultaneously on the netlist and parse tree level. DeFacTo received Verific’s HDL Component Software package, including an RTL database written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms for both 32- and 64-bit compilers. Following Verific’s standard business model, the package was licensed to DeFacTo as source code, and DeFacTo has access to Verific’s comprehensive online support and maintenance.
DeFacTo of Moirans (near Grenoble), France, and Palo Alto, Calif., will enable designers to plan, analyze and implement IC test logic before synthesis. It will deliver a high-quality tool suite covering all DFT needs working at the RT level through Verific’s HDL Component Software.
Says Philippe Duchene, DeFacTo’s vice president of engineering: “We were immediately impressed with the range of Verific’s customers, many of whom are our EDA partners. It became clear early in our relationship that Verific’s products and support team are equally impressive. It’s been an extremely rewarding joint technical development effort.”
“DeFacTo is a company that we are proud to have as a customer,” adds Michiel Ligthart, Verific’s chief operating officer. “Its exciting, breakthrough technology will soon give chip designers a new way to add test logic to their designs.”
Verific will demonstrate its HDL Component Software in Booth #3464 during the 44th Design Automation Conference (DAC) June 4-8 at the San Diego Convention Center in San Diego, Calif.
About Verific Design Automation
Verific Design Automation was founded in 1999 by electronic design automation (EDA) industry veteran Rob Dekker. It develops and sells C++ source code-based SystemVerilog, Verilog and VHDL front ends — parsers, analyzers and elaborators — as well as a generic hierarchical netlist database for EDA applications. Verific’s technology has been licensed in many applications, combined shipping more than 45,000 end-user copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: firstname.lastname@example.org.