Renesas Verifies Single Chip Mobile Processor with ArchPro Solutions

ArchPro Design Automation announced that Renesas Technology Corp. used their solutions to achieve requirement of verification on their latest 90nm single chip mobile processor. Renesas Technology Corp. is one of the world’s leading semiconductor system solutions providers for mobile, automotive and PC/AV (Audio Visual) markets and the world’s No.1 supplier of microcontrollers.

Renesas has not only combined multiple applications such as video telephony and 3D Java game on this design, but also allowed the flexibility to support a number of standards such as WCDMA, GSM/GPRS. The single chip mobile processor design supported an integration of multiple processors and also a novel power scheme to control power required to realize the integration. The power reduction strategies included multiple voltages and power gating. These schemes imposed additional requirements in terms of operating modes and mode transitions. ArchPro’s tools and expertise were instrumental in verifying the functionality across all these different power modes and transitions. Renesas also found that ArchPro Solutions fit well with Renesas’ design and verification flow.

Yoshio Inoue, chief engineer of DFM & Digital EDA technology Development Dept. at Renesas Technology Corp. said, “The single chip mobile processor has the most complex functionality with the lowest power consumption.” Mr. Inoue continued, “ArchPro solutions not only verified our power scheme at RTL level, but also helped us debug some complex problems after the netlist was generated. They really helped us get to the sign-off. We are pleased with their performance and the seamless integration with our tool flow.”

“We are pleased with the success achieved by Renesas by using ArchPro solutions,” said Pratap Reddy, CEO of ArchPro. “ArchPro is helping customers like Renesas in the area of multi-voltage verification. This area is poised for a huge growth and ArchPro is giving the designers flexibility to use multiple low power techniques on a single design without losing the functionality.”

ArchPro’s Multi-Voltage Solutions
ArchPro solutions help designers accelerate multi-voltage designs while using an existing familiar flow. The solutions include, MaVeric(TM), comprehensive multi-voltage verification solution, MVSIM, co-simulator for verification of power-managed designs; MVRC, multi-voltage rule checker; and MVSYN, automating the implementation of multiple voltage designs. ArchPro solutions have reached maturity with the following achievements:

  • Top-tier customers world-wide using ArchPro solutions for verifying multi-voltage designs
  • Silicon proven on 20+ complex low-power designs spreading across a spectrum from wireless to wired designs
  • Proven across multiple process nodes including 90nm and 65nm with design sizes of 200M transistors
  • Only solution that has verified advanced power reduction techniques such as power gating, substrate biasing and Dynamic Voltage Frequency Scaling

About ArchPro
ArchPro provides EDA products to meet low-power and multi-voltage power management challenges facing SoCs at 90nm and below. Having launched many of the world’s first EDA products for power-managed, multi-voltage, low-power design environments that allow for design simulation, verification, and implementation prior to silicon spins, ArchPro is paving the way toward reducing cost, risk, and time-to-market for chip designers. ArchPro is a member of Accellera, ARM(R) Connected Community, IEEE P1801 Working Group, Mentor Graphics VAP program, Si2 Low Power Coalition, and Synopsys in-Sync program. Recently, ArchPro also joined Virage Logic’s VIP program. Privately-held ArchPro is based in San Jose, Calif.