Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, announced that Japan’s Semiconductor Technology Academic Research Center (STARC) has selected Si2′s Common Power Format (CPF) in the development of STARC’s Low Power “PRIDE” reference design flow v1.5. STARC is targeting this low-power flow, for release to its member companies in October 2007, using technologies from the Cadence Logic Design Team Solution as well as the Cadence advanced-verification and digital-implementation solutions.
STARC recently completed a feasibility study and validated a CPF-based low-power flow using a test design. STARC engineers performed physical prototyping confirming significant benefits of CPF-based low-power design flow when tested against a non-CPF flow. STARC expects their member companies to realize 50 percent reduction in turn-around time, early low-power architectural explorations and greater design reusability.
CPF is a design specification language that addresses the limitation in traditional design-automation-tool flows by capturing the designer’s intent for power management and by enabling the automation of advanced power-lowering design techniques. By preserving low-power design intent throughout the design, the solution eliminates laborious manual work, reduces power-related chip failure and provides power predictability early in the design process. CPF v1.0 is available as a Si2 standard to the industry at large.
“STARC is responding to increasing requests from our member companies for an advanced low-power solution,” said Nobuyuki Nishiguchi, vice president and general manager of STARC. “Our low-power flow using CPF will not only provide a fully integrated design, verification and implementation methodology, but also offers a new environment for low-power architectural exploration in the early design stages and reduced turn-around time.”
“Selection of the Common Power Format by STARC to enable their new low-power flow is a strong reflection of the maturity, use model, and adoption of CPF as a practical power format within the design community,” said Jan Willis, senior vice president, Industry Alliances at Cadence. “STARC’s leadership in developing an integrated methodology will enable their member companies to deliver low-power products in volume and will enhance the productivity of a broad base of designers.”
The Semiconductor Technology Academic Research Center, STARC, is a research consortium co-founded by major Japanese semiconductor companies in December 1995. STARC’s mission is to contribute to the growth of the Japanese semiconductor industry by developing leading-edge, system-on-chip (SoC) design technologies.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
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