Genesys Testware, Inc., a leading supplier of yield, quality and cost optimization tools for nanometer ICs, announced the addition of a graphical user interface (GUI) to its embedded test tool ChiptestMaker(TM). Currently IC designers develop long and complex scripts for their embedded test tools to embed test structures into a System IC. ChiptestMaker(TM) also automates the process of verifying and inserting test structures into an IC design. This process utilizes logic synthesis and digital simulation tools from Cadence, Synopsys and Magma. The new graphical interface to ChiptestMaker(TM) improves designer productivity by eliminating scripting and enforcing a flow.
ChiptestMaker is a suite of two tools for IC designers – ArraytestMaker(TM) and HiertestMaker(TM). ArraytestMaker(TM) helps system IC designers to optimize yield and quality of embedded memories (SRAM, CAM). HiertestMaker(TM) helps system IC designers to optimize quality of inter-chip and intra-chip wiring (Boundary scan). The GUI employs a step-by-step wizard like interface to walk IC designers through each step in the process. This enables IC designers to focus on high level requirements for embedded test and boundary scan instead of low level tool minutiae. It enforces a rigorous flow with automated verification at each step to make embedded test development both predictable and repeatable. System IC’s typically require several iterations of design implementation due to bug fixes. Therefore fast incremental embedded test development is required. The GUI also supports efficient incremental embedded test development by requiring the re-execution only of those embedded test development steps that are affected by the design change.
“The time to get started on adding embedded test circuits to a design has been reduced from weeks to hours using the ChiptestMaker GUI,” said Vinod Sutrave, President of Network Silicon, Inc., a leading IC design services company. “It eliminates the need to consult the User Manual since a bubble help is available for each field in each form in the GUI.”
“Design managers can minimize schedule risk for embedded test development, without compromising test effectiveness using the ChiptestMaker GUI”, said Bejoy Oomman, President of Genesys Testware. “Now a specialist in DFT or BIST or JTAG is not required to optimize the quality and cost of a System IC through effective embedded test.”
The GUI is available at no additional cost to existing users of ChiptestMaker(TM) now.
This new tool will be demonstrated during the upcoming 44th Design Automation Conference that will be held from June 4-7, 2007 at the San Diego Convention Center, San Diego, California in Exhibitor Booth #5863.
About Genesys Testware
Genesys Testware, Inc. provides tools to improve yield, quality and cost of nanometer ICs. Its products are all silicon-proven in various customer designs. Genesys Testware’s corporate headquarters are located at 76 Whitney Place, Fremont, CA 94539.
ArraytestMaker is a trademark of Genesys Testware, Inc.