CLK Design Automation introduced the Amber(TM) Analyzer, the industry’s first true threaded and incremental static timing and signal integrity (SI) analysis solution. The company’s patent-pending architecture enables the Amber Analyzer to leverage the power of multi-core, multi-processor compute platforms to execute 10 to 20 times faster than conventional tools. The same architecture also enables true incremental analysis for timing and signal integrity. Incremental analysis increases throughput by 100 times or more over existing design flows without any compromise in accuracy.
Timing and performance analysis is one of the biggest bottlenecks in the physical implementation flow for high performance, nanometer designs. One signal integrity run can literally take 24 hours or more on a 10 million-instance design. With most design teams running at least 20 metal/process/mode corners, analysis can run for a week. This problem is further compounded by late-stage ECOs (engineering change orders). A simple ECO, for example changing one net to repair a crosstalk problem, forces another 24-hour analysis run. The Amber Analyzer removes these barriers to achieving design closure with its use of threading compute methods, its ability to support true incremental analysis, and its robust functionality for a wide range of analysis tasks.
“Amber is a true next-generation static analysis platform,” said Isadore Katz, president and CEO of CLK Design Automation. “The key is the architecture. Starting from the ground up with a threaded, incremental architecture is the only way to deliver static analysis solutions that will scale with compute platforms and customer designs. It reduces a considerable bottleneck in the IC design process and gives designers both the performance and features they need to deal with today’s largest, most complex designs.”
CLK Design Automation will debut the Amber Analyzer at the 44th Design Automation Conference to be held June 4-8, 2007 in San Diego, Calif. Attendees can see the Amber product overview in Booth #5671 or email email@example.com to pre-arrange for private demonstration.
Next-Generation Architecture: Threaded and Incremental
Threading uses the horsepower of the new multi-core, multi-CPU computing platforms being delivered today to improve tool performance. The Amber Analyzer is the first static timing and signal integrity tool that is fully threaded — from reading designs, calculating delay and crosstalk, to generating reports. With the Amber platform, signal integrity analysis of a 10-million instance design runs in two hours front-to-back on a four-CPU system (eight cores total). On an eight-CPU (16 cores) system, the same design runs in slightly more than an hour. The performance of the Amber tool scales linearly with the number of CPUs at least up through 64 cores.
The Amber Analyzer is fully incremental across all classes of analysis (timing, signal integrity, leakage) for any type of design change, such as cells swaps, netlist modifications, constraints, or parasitics. For example, a 50,000-cell swap on the same 10-million instance design takes less than three minutes to analyze for signal integrity. Most importantly, the Amber incremental capability guarantees that designers will get exactly the same answer as if they had run the entire design flat. Moreover, the memory footprint for the analysis is proportional to the change. Incremental analysis can be run with desktop class machines.
The Amber paradigm of faster, more comprehensive analysis does not compromise the accuracy of results. The base delay analysis is within one percent of other timing analysis tools, while the signal integrity analysis is within three percent of SPICE. The Amber platform offers the full range of analysis options that include timing, signal integrity, statistical timing, leakage and statistical leakage.
In addition to performance and methodology benefits, the Amber solution offers new functionality that designers have been asking for with static analysis solutions. Amber is inherently multi-corner and multi-mode. This enables engineers to efficiently analyze timing and signal integrity across all operating conditions simultaneously. It has a persistent database for the design and analysis results, along with an experiment layer that allows multiple users to interact and debug timing results, as well as perform what-if analysis and diagnostics. It features an open C-based application programming interface (API) that allows users to incorporate the Amber Analyzer into their own tools, or to develop specialized add-on tools or optimizers. Finally, it is script compatible with existing tools and provides the ability to generate custom reports.
Pricing & Availability
The Amber Analyzer was designed and developed in conjunction with major semiconductor companies, and has been verified against multiple production, nanometer designs. It is shipping today for 32-bit and 64-bit Linux computing platforms and priced starting at U.S. $25,000 for a one-year license.
CLK Design Automation, Inc. develops and markets static timing and power analysis solutions used in the design of high-performance microprocessor and advanced semiconductors. Its fully threaded, incremental architecture pioneers a new generation of electronic design automation (EDA) tools that enables the CLK Amber Analyzer to execute 10 to 100 times faster than conventional analysis tools. Headquartered in Littleton, Mass., the company was founded by EDA industry veterans and has received $9 million in venture funding to date.
Amber is a trademark of CLK Design Automation.