ArchPro Joins Virage Logic's VIP Program

ArchPro Design Automation announced that it has joined Virage Logic’s VIP partnership program. This program enables both companies to share their technology in an effort to find better solutions for multi-voltage challenges faced by the design community.

Using multiple voltages is becoming a common design practice to reduce dynamic power, active leakage and standby leakage. As techniques like power gating, low-Vdd standby, dynamic voltage frequency scaling and back bias become common, designers are increasingly faced with challenges such as IP modeling and verification. The partnership between ArchPro, a pioneer in multi-voltage verification and Virage Logic, a leader in low power IP design, can help designers address these challenges.

“We are pleased to welcome ArchPro into our VIP program,” said Mary Ann White, Director of Business Development, Virage Logic. “As a leading supplier of low power semiconductor IP for nearly a decade, working closely with an EDA partner like ArchPro helps deliver integrated solutions for our mutual low power customers.”

“We are glad to join the Virage Logic’s VIP program,” said Anand Iyer, Senior Director of Marketing, ArchPro Design Automation. “ArchPro has proven itself in multi-voltage verification. Our support of Virage Logic’s world-class low power IP opens new solutions for the customer in terms of power reduction.”

ArchPro’s Multi-Voltage Solutions
ArchPro solutions help designers accelerate multi-voltage designs while using an existing familiar flow. The solutions include, MVSIM, co-simulator for verification of power-managed designs; MVRC, multi-voltage rule checker; and MVSYN, automating the implementation of multiple voltage designs. ArchPro solutions have reached maturity with the following achievements:

  • Top-tier customers world-wide using the solutions for verifying multi-voltage designs
  • Silicon proven on 20+ complex low-power designs spreading across a spectrum from wireless to wired designs
  • Proven across multiple process nodes including 90nm and 65nm with design sizes of 200M transistors
  • Only solution that has verified advanced power reduction techniques such as power gating, substrate biasing and Dynamic Voltage Frequency Scaling

About ArchPro
ArchPro provides EDA products to meet low-power and multi-voltage power management challenges facing SOCs at 90nm and below. Having launched many of the world’s first EDA products for power-managed, multi-voltage, low-power design environments that allow for design simulation, verification and implementation prior to silicon spins, ArchPro is paving the way toward reducing cost, risk, and time to market for chip designers. ArchPro is a member of ARM(R) Connected Community, Synopsys InSync program, Mentor Graphics VAP program, IEEE P1801 study group, Si2 Low Power Council and Accellera. Privately held ArchPro is based in San Jose, Calif.