DAC Features UML for SoC Design Workshop

The Design Automation Conference (DAC), the electronic design automation (EDA) industry’s premier event, announced the Fourth International Workshop for Unified Modeling Language(TM) (UML) for System-on-Chip (SoC) Design will be held Sunday, June 3, from 9 a.m.-5:30 p.m. at the San Diego Convention Center during the 44th DAC. Featuring designers from around the globe, the workshop will provide attendees an opportunity to share experiences, exchange information and discuss the latest applications of UML in SoC design.

Keynotes by Jeremy Goulding, CEO of ARTiSAN Software, a UML tool vendor providing support for automatic SystemC code generation from UML models, and W. Mueller, co-editor of “UML for SoC Design” (published in 2006 by Springer-Verlag), will open the morning and afternoon sessions. Nine other presentations, selected from carefully reviewed submissions, will explore embedded system analysis, design, modeling, synthesis and design flows supported by UML. Seven product demonstrations from tool vendors and academic and industrial users will take place during the afternoon coffee break to highlight UML as a system-level visual language for specifying, analyzing, designing and verifying SoCs. Attendees will have the opportunity to participate in a live survey. The workshop organizers will moderate a discussion at the end of the day.

Organized by John Wolfe of Mentor Graphics Corp., Bruce P. Douglass of Telelogic, and Yves Vanderperren from Katholieke Universiteit Leuven in Belgium, the UML workshop is open to anyone interested in learning more about UML for SoC Design. Registration is $100 for members of ACM or IEEE and $150 for non-members.

About DAC
The Design Automation Conference (DAC) is the premier educational and networking event for Electronic Design Automation (EDA) and silicon solutions. More than 11,000 designers, developers, researchers, academics and managers from leading electronics companies and universities from around the world attend. DAC features close to 60 technical sessions covering the latest research on design methodologies and technologies, EDA developments and trends selected by a diverse committee of electronic design experts. A highlight is its Exhibition and Suite area with approximately 250 of the leading and emerging EDA, silicon and IP providers.

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