Synopsys, Inc. (Nasdaq: SNPS), a world leader in semiconductor design software, announced that Open-Silicon, a leading supplier of predictable, reliable and cost-effective ASIC solutions, has adopted Synopsys’ DFT MAX scan compression solution to substantially reduce the cost of testing ASICs. DFT MAX lowers test costs by significantly reducing the amount of time and data required to test digital circuits. Open-Silicon requires scan compression solutions for 130-, 90- and 65-nanometer (nm) designs that are easy to implement and have minimal impact on their established design flows. Using DFT MAX, Open-Silicon’s design team easily achieved a 90-percent test application time reduction for scan testing. The ease of implementation and predictable results solidified Open Silicon’s decision to adopt DFT MAX for use with its existing Galaxy(TM) Design Platform flows.
“Optimizing costs is a key element to the success of our OpenMODEL services,” said Dr. Satya Gupta, vice president of Engineering at Open-Silicon. “We carefully evaluated many different aspects of the Synopsys DFT MAX scan compression solution, from the way it performed with different compression parameters to its effect on downstream flows and fault coverage. In all aspects, DFT MAX produced results to our satisfaction: the tool substantially reduced test time and test data volume with very low gate/routing area and timing impact. We anticipate these capabilities will yield significant benefits for our customers.”
DFT MAX utilizes advanced scan compression technology to substantially reduce both test application time and test data volume compared with traditional scan techniques. DFT MAX’s key advantage is that it is easy to implement and is far less intrusive on design flows and design performance than alternative methods. Fragmented, bolt-on flows requiring separate design synthesis and test compression insertion steps can break critical timing, add routing congestion and necessitate subsequent re-optimization. In contrast, DFT MAX is integrated with the Galaxy RTL, physical and sign-off design flows to help eliminate costly, time-consuming design iterations between synthesis and physical implementation. Simultaneously, designers can achieve convergence of timing, power, area and test.
“Today, successful fabless ASIC companies are differentiated by their ability to embed high reliability into their products while remaining competitive on price,” said Graham Etchells, director of Test Automation Marketing at Synopsys. “Open-Silicon’s decision to adopt DFT MAX is a clear indication that Synopsys has the portfolio of products and solutions to enable our customers to meet these challenges and achieve their business goals.”
Open-Silicon, Inc. is a fabless ASIC company delivering the most cost-effective, predictable and reliable custom ASIC solution to electronics product customers worldwide. Open-Silicon’s OpenMODEL(TM) is the semiconductor industry’s first end-to-end custom ASIC solution based on a revolutionary business model that provides a seamless, low-cost, low-risk alternative to traditional models for complex ASIC design and development. For more information, call 408-240-5700.
Synopsys, Inc. is a world leader in EDA software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia.
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