Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), announced the availability of design cores and verification IP which support the preliminary I/O virtualization (IOV) specifications from the PCI-SIG. IOV is a key technology that enables systems to simultaneously share PCI Express (PCIe) resources within multi-CPU systems, or across multiple operating systems. Vendors are now architecting data centers and large storage environments that use IOV technology to increase performance and reduce overall power and system costs. Denali’s Databahn(TM) PCIe IOV cores and PureSpec(TM) PCIe verification IP products are now being used by developers to accelerate the design and verification of these systems, and speed overall deployment of PCI Express IOV technology.
“With the growth of computational power and the number of servers in storage environments, technologies to support current and future requirement for high-speed connectivity, such as IOV, becomes a critical requirement,” remarks Jag Bolaria, senior analyst at The Linley Group. “Denali is paving the way with its IP solutions for PCI Express IO Virtualization technologies.”
Denali’s Databahn PCIe IOV cores and PureSpec PCIe verification IP products provide full support of the Address Translation Service specification, Single-Root I/O Virtualization specification, including physical and virtual function (VF) configuration spaces, VF Alternate Routing-ID, and Functional Level Reset (FLR) capabilities. These features will be highlighted at the PCI-SIG Developers’ Conference, May 21-22 in San Jose, CA, by Denali’s systems architect, Anujan Varma. Mr. Varma is scheduled to present two papers on advanced PCI Express technologies, including “LTSSM Implementation at 5Gb/s and Beyond” and “Single Root IOV Endpoint Implementation,” which is based on an actual reference implementation of the IOV specification.
“Our pre-silicon PCIe virtualization solutions represent significant cost and time-saving potential without jeopardizing our customers’ high performance requirements,” remarks David Lin, vice president of product marketing for Denali. “Our customers depend on high-quality design and verification IP solutions that are inline with the developing trends with the PCI Express technology.”
About PureSpec PCIe Verification IP
PureSpec is the most widely used VIP product for PCIe technology with over 250 PCIe designs validated. All PureSpec products are directly integrated into all popular EDA languages and verification environments including: Verilog, SystemVerilog, VHDL, Cc/C++, SystemC, ‘e’, OpenVERA. Quality, completeness and seamless integration with all modern verification environments make PureSpec the solution of choice for functional verification and interoperability validation of PCIe designs.
About Databahn PCIe Design IP
Databahn PCIe is a high-quality design IP product that reduces risk and speeds time-to-market for deploying PCIe interfaces in silicon. The Databahn PCIe core has been implemented in production silicon and successfully deployed in several leading OEM server products as well as extensively tested with all major chipsets and motherboards. The Databahn PCIe core supports the latest PCI-SIG 2.0 specifications and has been utilized in several customer tapeouts.
About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry’s most trusted solutions for deploying PCI Express, NAND and DRAM subsystems. Developers use Denali’s EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Palo Alto, California and has offices around the world to serve the global electronics industry.
Denali and Denali Software are registered trademarks of Denali Software, Inc. Databahn and PureSpec are trademarks of Denali Software, Inc. PCI Express is a registered trademark of PCI-SIG.