The increase in analog and mixed-signal (A/MS) content of systems on chip (SoCs) and integrated circuits (ICs) is causing a disproportionate number of chip respins. At the same time, verifying circuit performance in a mixed-signal environment is becoming more complex and more critical to yield and cost control. Kimotion Technologies Inc. unveiled a new technology to allow A/MS circuit and system designers to build performance models that enable much more thorough optimization and verification of yield and performance issues than has been possible with existing verification flows.
The transition from traditional corner-based design methodologies to flows using detailed statistical distributions of individual technology variables, coupled with the integration of analog and digital parts on a single chip, has created a growing need for technology that automatically verifies and optimizes a circuit’s yield across statistical process variations. Process variability and shrinking supply voltages combine to reduce voltage headroom and make A/MS circuits more sensitive to fluctuations in process and environment.
The traditional way to verify the robustness of A/MS designs over process and environment variations is to run a Monte Carlo analysis on transistor-level descriptions. “This is a slow and inefficient approach,” said Oscar Buset, president of Kimotion. “What design teams need is a way to build models from existing descriptions, within existing flows, to capture the influence of process and environmental variations accurately. By leveraging existing setups, Kimotion enables designers to limit the sampling of process variations to build models and to seriously reduce the number of simulations required for Monte Carlo runs.”
“We recently used Kimotion’s calibrated behavioral modeling techniques to solve a tough PLL design problem,” said Harry Peterson, senior director of IC technology at Pixelworks, Inc. “This PLL is the critical element in a SerDes (serializer/ deserializer) that has to work with good margins and while drawing minimal power. Kimotion enabled us to reduce simulation time for the PLL by a factor of 240, and the error during the calibration process was controlled to within 2% relative to the nominal parameter values. Efficient simulation was essential since we had to verify that the PLL met the imposed specifications across all process and environmental variations.”
Kimotion’s technology allows circuit designers to model, verify and optimize their analog/mixed-signal circuits. Models can be built incrementally to a desired level of accuracy with a very small number of simulations, and can be used either in a classic Monte Carlo flow, replacing the simulations, or by Kimotion’s verification and optimization technology, helping designers not only to identify potential problems before going to silicon, but also to correct them.
Kimotion technology is in the hands of key customers and partners. The company will be demonstrating its technology in Booth 7382 at the Design Automation Conference (DAC) in San Diego, California, from 4 June to 7 June, 2007.
Kimotion allows circuit and system designers of analog and mixed-signal ICs to build performance models that enable much more thorough verification of yield and performance issues than has been possible with existing verification flows. The company’s technology fits into any design flow, reducing the risk of respins and overdesign by enabling designers to model, analyze, optimize and verify your circuits under environment and process variations.