Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, announced the industry’s first kit that enables engineers of different experience levels to adopt advanced low-power techniques with minimized risk and deployment effort. A complement to the Cadence(R) Low-Power Solution, the Cadence Low-Power Methodology Kit provides a working end-to-end methodology covering logic design, functional verification and physical implementation. The Kit includes example IP, scripts and libraries; all proven on an included wireless segment representative design. Delivered together with Cadence applicability consulting services, the Kit enables design teams without extensive low-power implementations to quickly optimize their low-power design environment, and accelerate their time to lower power, more competitive system-on-chip products.
The Cadence Low-Power Methodology Kit contains a generic wireless application design, implemented using multi-supply voltage and power shut-off methods, and all associated command scripts and technology files needed to carry the design through the entire end-to-end flow. The example IP in the design is from Cadence and third parties including ARM(R) processor and AMBA(R) on-chip communication technology, WiFi from Wipro, USB 2.0 from ChipIdea, 65-nanometer ultra low-power memories from Virage Logic and 65-nanometer technology libraries from TSMC.
“The Cadence Low-Power Methodology Kit allowed us to reduce the turnaround time for implementing and verifying a low-power solution for our design,” said Dr. Samuel Sheng, CTO of Telegent Systems. “The Kit simplified both the logical and physical implementation for our design; we plan to use it in our future tape outs. Having access to such Kits is a great benefit as they allow users to leverage and adapt proven solutions quickly and with minimal risk.”
“The semiconductor industry needs to speed up deployment of low-power methods,” said Craig Johnson, corporate vice president for Marketing and Strategy at Cadence. “The systems markets, especially wireless and consumer, demand it. While some IC companies have already completed large numbers of sophisticated low-power tapeouts, many others are still tuning or even establishing their infrastructure and know-how. The Cadence Low-Power Methodology Kit directly addresses this problem; it helps low-power teams deploy optimized, highly automated low-power design flows quickly across multiple engineering groups for maximum productivity.”
The Low-Power Methodology Kit is modular and includes six distinct flows: low-power functional simulation, logic synthesis, design for test and ATPG, physical design, formal implementation, verification and power grid signoff. Users can implement the entire Kit as an integrated flow, or may select modules individually. The Si2 Common Power Format standard is used to provide a single specification of low-power intent throughout the flow.
“Power has become a critical success factor for our customers and a key differentiator for our communication IP, like our 802.11 WiLD(TM) IP that Cadence embedded in its Kit,” said Mana Coste, director marketing for Wipro-NewLogic. “We are pleased to see Cadence take the lead in the industry, enabling delivery of easily integrated low-power IP solutions.”
“Integration and reuse of IP in a low-power environment creates new challenges not easily solved using traditional approaches for our customers and their design processes,” said Ian Drew, vice president, Segment, ARM. “Through the Kits initiative, Cadence is directly addressing these challenges, which support our mutual customers.”
Cadence Kits enable IC designers to accelerate technology-specific product development and address design challenges in EDA technology segments such as analog mixed signal, silicon-in-package (SiP), coverage-driven functional verification, and radio frequency integrated circuit (RFIC). By using Cadence Kits, customers can focus more of their design resources on design differentiation rather than developing design infrastructure.
Cadence(R) enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Cadence is a registered trademark, and the Cadence logo is a trademark of Cadence Design Systems, Inc. in the U.S. and other countries.
ARM is a registered trademark of ARM Limited. All other brands or product names are the property of their respective holders. “ARM” is used to represent ARM Holdings plc; its operating company ARM Limited; and the regional subsidiaries ARM INC.; ARM KK; ARM Korea Ltd.; ARM Taiwan; ARM France SAS; ARM Consulting (Shanghai) Co. Ltd.; ARM Belgium N.V.; AXYS Design Automation Inc.; AXYS GmbH; ARM Embedded Solutions Pvt. Ltd.; ARM Physical IP, Inc.; and ARM Norway, AS.