Bluespec(TM) Inc. and EVE announced immediate availability of an integrated solution of electronic system level (ESL) synthesizeable transactors and models that run directly on EVE’s hardware-assisted verification platforms. The link between Bluespec’s ESL synthesis and EVE’s ZeBu hardware-assisted verification platform of accelerators, emulators and field programmable gate array (FPGA) prototypes offers high simulation speed with hardware accuracy early in the development cycle for architectural exploration, virtual prototyping, modeling and verification. The result is a single development environment for models, transactors, implementations and synthesizable verification testbenches, and a rich foundation library of intellectual property (IP).
“This changes the game completely,” remarks Shiv Tasker, chief executive officer (CEO) of Bluespec, developer of the only ESL synthesis for control logic and complex datapaths in chip design. “Design teams can derive value from using ESL synthesis immediately by simulating at hardware speeds, no matter how complex the system on chip.”
Typically, the trade-off between simulation speed and hardware accuracy hinges on the availability of a register transfer level (RTL) model that is usually available late in the development cycle. Additionally, RTL simulation speed is slow, except when emulation, hardware acceleration or FPGA prototyping is used, but these are only effective with mature, relatively bug-free RTL code. High-level functional models may be relatively fast, but typically aren’t hardware accurate.
Normally, transactors, models and implementations are handled byby three separate environments. Transactors and models are usually not synthesizable. Models running on emulation, hardware acceleration or prototyping platforms require RTL implementations and require mature, relatively bug-free RTL code to be effective.
“This is a much better validation environment than a pure software simulation flow,” remarks Luc Burgun, CEO and president of EVE, supplier of the broadest selection of hardware-assisted verification solutions including acceleration, fast emulation and prototyping. “By using consistent models for architectural exploration and implementation, the entire validation process can be dramatically improved.”
The availability of synthesizable transactors and ESL models from Bluespec and EVE allows a seamless, heterogeneous mix of models, implementations, a verification testbench and software models connected through transactors. The rapid plug-and-play construction of a system is accomplished through synthesizable IP — transactors optimized for EVE, system building blocks and models, the Bluespec AzureIP Foundation Library and verification IP — and ESL Synthesis capabilities, such as self-checking interfaces and static verification. Transactors are synthesizable, used at the transaction-level of design and are parameterized on any high-level data type, including structures and unions.
In a related announcement, Bluespec today said it has added system-level building blocks to its AzureIP(TM) Foundation Library, a family of pre-packaged and verified IP and design reuse capabilities to accelerate ESL design and verification. (See news release dated May 7, 2007, titled: “Bluespec Adds System-Level Building Blocks to AzureIP Foundation Library.”) New blocks include ARM(R) AMBA(R) AXI(R) and AHB and Open Core Protocol (OCP)-IP interface bus component libraries comprising parameterized bus structures, bus interface transactors and data type libraries.
Bluespec will demonstrate its entire product line of ESL Synthesis Solutions in Booth #6963 during the 44th Design Automation Conference (DAC) June 4-7 at the San Diego Convention Center in San Diego, Calif.
Pricing and Availability
Transactors and models have been added to Bluespec’s AzureIP Foundation Library that includes a rich family of building blocks and comes standard with Bluespec’s ESL Synthesis.
Bluespec Inc. manufactures industry standards-based Electronic Design Automation (EDA) toolsets that significantly raise the level of abstraction for hardware design while retaining the ability to automatically synthesize high-quality RTL, without compromising speed, power or area. The toolsets, the only ones focused on control and complex datapaths, allow ASIC and FPGA designers to reduce design time, bugs and re-spins that contribute to product delays and escalating costs. More information can be found by calling (781) 250-2200.
Bluespec and Azure IP are trademarks of Bluespec Inc.