Chip Estimate Rolls Out InCyte for Pre-RTL Performance Analysis

Chip Estimate Corp. announced the release of technology that enables performance analysis at the earliest phase of the chip design cycle. The flagship InCyte(TM) product now provides users quantifiable feedback regarding the feasibility of achieving various performance targets for their chip. The new analysis capability is technology node, process and IP specific. Users can now make better decisions regarding chip architecture tradeoffs to minimize the risk of missing performance goals, and to push the limits of technology with greater success.

In addition, the company also announced that other significant features have been added to InCyte that increase the utility of the early chip planning system and strengthen EDA design flow integration.

New Technology Overview

  • Performance Analysis – Users can now get quantified feedback on the likelihood of achieving performance goals for a given chip specification, targeted at a specific manufacturing process. InCyte provides a range of frequencies achievable and recommendations on logic depth.
  • Connectivity Definition – The interconnectivity of IP and other design components within a chip can now be incorporated into design specifications enabling more accurate chip planning and estimation. Connectivity provides significant enhancements to the generation of design data which can then be leveraged by IC implementation tools.
  • Block Diagramming – Design teams can now communicate their architectural specifications visually into InCyte with the ease of use of a tool like Microsoft Visio. Users simply drag and drop IP and other design components into block diagrams that InCyte uses to estimate the size, power and cost of the resulting chip.
  • Design Flow Integration – Design specification data now links directly into leading EDA implementation flows from vendors including Cadence, Magma, Mentor Graphics and Synopsys. By coupling design specifications and IP data, InCyte now outputs design data files, such as specific scripts and wrappers to automatically feed design plans into industry standard file formats and EDA implementation tools. Users have a streamlined path from their design size, power and cost estimation to convergence in final silicon.
  • IP Library Selection – InCyte helps guide user selection of IP libraries and provides quantified feedback on the particular density, power, leakage and performance of a given library. The software ships with models for hundreds of popular 3rd party IP libraries accessible at the click of a button and also supports internally developed IP.

InCyte at DAC
This technology will be demonstrated at the Design Automation Conference (DAC) in San Diego, California June 4 – 8.

Price and Availability
InCyte starts at US $35,000 and is available immediately.

About Chip Estimate Corporation
Chip Estimate Corporation is an EDA company that delivers streamlined access to integrated chip project planning solutions. The company develops and markets the InCyte chip estimation systems, into which it integrates IP and manufacturing process models for the most accurate chip estimation possible. InCyte Enterprise(TM) is a recipient of a 2007 International Engineering Consortium DesignVision Award. Chip Estimate partners with leading IP vendors and semiconductor manufacturers who share our mission of early and accurate chip planning for our mutual customers’ ultimate design success. Since the 2005 launch of, over 10,000 users have performed over 50,000 chip estimations with InCyte. The company is headquartered at 10050 North Wolfe Road, Suite SW1-266, Cupertino, Calif. Telephone: 408 255 0444. Facsimile: 408 255 0344. Email:

InCyte, InCyte Enterprise and are registered trademarks of Chip Estimate Corporation.