The IEEE VLSI Test Symposium, a leading test industry technical event, celebrates its 25th anniversary next week, from May 6th to May 10th in Berkeley, California. The 2007 edition of VTS features a strong technical program designed to address key challenges in the areas of manufacturing test, design-for-test, and validation of integrated circuits and systems. The VTS 2007 technical program, assembled by a committee that was led by Prof. Alex Orailoglu, VTS Program Chair and Professor at the University of California at San Diego, CA, features technical sessions on all aspects of test, including test generation & flows, test quality, diagnosis, yield analysis, nanoscale testing, RF, analog & mixed-signal test, wireless testing, flash & memory test, power issues in test, and secure IC test.
“The VTS program committee has put together an exciting technical program,” said Prof. Paolo Prinetto, General Chair of VTS 2007, and Professor at Politecnico di Torino, Italy. “VTS provides a great opportunity for attendees to explore the frontiers of test technology and get a glimpse of emerging test trends.”
This year’s keynote address titled “New Role of Test in 45 Nanometer,” will be delivered on Monday, May 7th, by Dr. Antun Domic, Senior Vice President and General Manager, Implementation Group, Synopsys. A second keynote address titled “Roadmap of Design,” will be presented on Monday, May 7th, by Gary Smith, noted EDA analyst and President, Gary Smith EDA.
An added attraction to the VTS program is the ‘Innovative Practices’ track, which will highlight cutting-edge challenges faced by test practitioners, and innovative solutions on topics such as Design in presence of variations, Small delay test, High speed test, Reliability in scaled CMOS, Open yield diagnostics solutions, New memory failure modes, Collaborative test practices, Board and system memory cluster test, and RF yield. “The innovative practices track provides a unique opportunity for attendees to get an in-depth understanding from their peers of current test issues and the best current practices to address them,” said Dr.Yervant Zorian, Chief Scientist, Virage Logic, Fremont, CA. “VTS has done a stellar job in organizing this special track to provide timely information to the practitioners of test.”
Building on the success of earlier years, workshops on allied areas of test – the Open Source Test Technology Tools Workshop and the Wireless Test Workshop, are co-located at VTS 2007. This year’s program also features full-day tutorials on Scan based Delay Testing of Nanometer SOCs, Dealing with Timing Issues for sub-100nm Designs, and DFX: The Convergence of Yield, Manufacturing, and Test. In addition, VTS will continue to offer a full schedule of panels, hot-topics sessions and embedded tutorials.
About The VLSI Test Symposium
The VLSI Test Symposium is a leading international forum where many of the world’s leading test experts and professionals from both industry and academia join to present and debate key issues in test technology. VTS was first organized in 1982 to focus attention on newly developing test technology, particularly ATPG and Design-for-Test. Since then, it has grown in size and scope to include tutorials, panels, and innovative practices. VTS enjoys the participation of attendees from all over the world, and each year solicits new contributions in areas of current interest to the semiconductor design and test community. VTS 2007 is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society’s Test Technology Technical Council (TTTC).