Apache Design Offers Power Analysis Technical Webinar

Apache Design Solutions, the leader in power signoff and complete silicon integrity platform solutions for system-on-chip (SoC) designs, announced that the company will present a free online technical webinar on how RedHawk, the industry’s defacto standard in SoC power sign-off, can provide designers with the ability to estimate, analyze, optimize, and validate their power grid design – from floor planning through silicon signoff. RedHawk is a complete SoC power and noise solution that has been adopted as a signoff solution by 80% of the top IDM, fabless semiconductor, and foundries, and is certified by TSMC’s reference flow 7.0.

Power Analysis Using RedHawk from Early Design to Signoff Webinar
An educational webinar detailing Apache’s comprehensive silicon integrity solutions for SoC power – spanning from early design to signoff.
10:00 a.m. PST, 1:00 p.m. EST
Wednesday, May 9, 2007

Specifically, this live webinar will discuss:

  • RedHawk’s capabilities and its application throughout different stages of the design flow
  • Methodology for early design analysis, including grid prototyping and decap optimization
  • Post layout power grid analysis and optimization, including impact on timing and design margin management
  • Examples of design analysis results and performance metrics.

About Apache Design Solutions
Apache delivers the leading power sign-off solution adopted by 80% of top semiconductor companies and a complete platform solution for silicon integrity of low-power, high-performance system-on-a-chip (SoC) designs. Apache’s innovative platform considers all sources of noise that impacts the design—such as power, signal, package / system IO, substrate, and temperature—Apache’s silicon integrity platform enables designers of leading networking, wireless, communication, consumer, and semiconductor companies to detect, fix, and prevent design weaknesses that can result in reduced yield or failed silicon. Apache’s vendor-neutral solution enables designers to adopt any industry-standard physical design flow and is certified by TSMC’s 5.0, 6.0, and 7.0 Reference Flow (NYSE:TSM).