Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, announced that the Industrial Technology Research Institute (ITRI) of Taiwan, and Ambarella Taiwan, have both adopted the Cadence(R) Encounter(R) VoltageStorm(R) power-analysis technology to enable leading-edge designs targeted for consumer electronics to meet their aggressive low-power specifications. Both companies implemented their design using the Cadence SoC Encounter(TM) RTL-to-GDSII system and looked to VoltageStorm dynamic and static power analysis to substantiate and verify the benefits of advanced low-power techniques, such as power gating, dynamic voltage-frequency scaling (DVFS) and multi-supply, multi-voltage (MSMV) scaling.
ITRI has developed a Parallel Architecture Core (PAC) digital-signal-processing chip with low-power and high-performance features for wireless communications and multimedia applications. The use of VoltageStorm power analysis to validate the success of its multi-voltage power-scaling techniques was critical to overall design success. The design was then implemented using the Cadence SoC Encounter RTL-to-GDSII system.
“We needed to minimize the power consumption for our latest DSP design, since the final application is a portable multimedia player,” said Dr. David Chang, deputy general director of SoC Technology Center (STC) of ITRI. “We used the SoC Encounter system to implement our advanced low-power design methodology, including DVFS, MSMV and power switching. VoltageStorm was used to verify the impact of power switches on both dynamic and static IR drop, and to validate that our power ramp-up times were within our engineering limits. VoltageStorm power analysis gave us valuable information that helped us validate and optimize our on-chip power delivery, and it is considered a valuable component of our signoff solution.”
Ambarella Taiwan, a pioneering company in portable hybrid digital camera VLSI designs, recently released a 90-nanometer hybrid digital H.264 video and image SoC. The 10-million gate design was created by using Cadence technologies. The chip consumed only 1.5 Watts and ran at 250MHz. VoltageStorm power analysis was used to verify IR drop hierarchically.
“We were very concerned about the impact of dynamic IR drop on our latest SoC chip,” said Chan Lee, vice president of VLSI at Ambarella. “If not managed effectively, we knew that IR drop could damage our silicon. VoltageStorm enabled us to optimize the power rails and increase the efficiency of the de-coupling capacitance, therefore minimize the dynamic IR drop. We were very pleased to see that VoltageStorm produced results that matched our engineering expectations and will continue to endorse VoltageStorm for our future tapeouts.”
A key component of the Cadence Low-Power Solution and a technology of the Encounter digital IC design platform, VoltageStorm dynamic and static power analysis is a comprehensive, hierarchical power rail verification solution for SoC designs that use a variety of advanced power management design techniques. Like all of the other components of the Cadence Low-Power Solutions, VoltageStorm is based on the Common Power Format (CPF). CPF is an Si2 industry standard format for specifying power-saving techniques in the design process enabling engineers to share and re-use low-power intelligence. The result is a power-analysis solution that comprehensively analyzes the complex low-power-management techniques typically used in today’s low-power designs.
“We are pleased to see VoltageStorm dynamic power analysis features continue to gain traction with leading customers and the further extension of its leadership position in static power analysis and verification,” said Dr. Chi-Ping Hsu, corporate vice president, IC Digital and Power Forward at Cadence. “As companies continue to employ state-of-the-art low-power techniques in their designs, a unified and integrated solution for design, implementation, and analysis is needed. Cadence Encounter Platform delivers a production and silicon-proven solution for advanced low power.”
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Cadence, VoltageStorm, and Encounter are registered trademarks and the Cadence logo and SoC Encounter are trademarks of Cadence Design Systems, Inc. in the United States and other countries.